Method for multilevel DRAM sensing

Details Method for multilevel DRAM sensing Method for multilevel DRAM sensing

1998-03-24

2000-11-21

Nelms, David

Static information storage and retrieval

Read/write circuit

Differential sensing

365196, 36518524, G11C 702

Patent

active

061512605

ABSTRACT:
A method for performing a sense and restore operation in a multilevel DRAM is described. The method describes the selective enabling of the sense amplifiers to operate at predetermined sensing thresholds. The multilevel DRAM stores two bits per cell using a four-voltage-level-per-cell system. Folded bitlines are divided into sub-bitlines each having dedicated sense amplifiers. The sense amplifiers are selectively enabled to operate at predetermined sensing thresholds to thereby greatly simplify the sense and restore operations. The circuit has standard CMOS bitline sense amplifier transistors connected thereto with pull down transistors that may be selectively enabled by switch signals. The length and width of these pull down transistors are varied to thereby effect the switching threshold of the sense amplifier.

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patent: 4841483 (1989-06-01), Furuyama
patent: 5119330 (1992-06-01), Tanagawa
patent: 5532955 (1996-07-01), Gillingham
patent: 5612912 (1997-03-01), Gillingham
patent: 5646900 (1997-07-01), Tsukude et al.
patent: 5701268 (1997-12-01), Lee et al.
A Sense and Restore Technique for Multilevel DRAM, Peter Gillingham, Jul. 1996, pp. 483-486.

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