Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-07-23
2004-12-07
Lebentritt, Michael (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S295000, C257S297000, C257S902000
Reexamination Certificate
active
06828610
ABSTRACT:
BACKGROUND
The present invention relates to information storage devices. More specifically, the present invention relates to memory devices including magnetic tunnel junctions.
A typical Magnetic Random Access Memory (“MRAM”) device includes an array of memory cells, word lines extending along rows of the memory cells, and bit lines extending along columns of the memory cells. Each memory cell is located at a cross point of a word line and a bit line.
The MRAM memory cells may be based on magnetic tunnel junctions (“MTJs”) such as spin dependent tunneling (“SDT”) junctions. A typical SDT junction includes a pinned layer, a sense layer and an insulating tunnel barrier sandwiched between the pinned and sense layers. The pinned layer has a magnetization vector that is fixed so as not to rotate in the presence of an applied magnetic field in a range of interest. The sense layer has a magnetization vector that can be oriented in either of two directions: the same direction as the pinned layer magnetization vector or an opposite direction of the pinned layer magnetization vector. If the magnetization vectors of the pinned and sense layers are in the same direction, the orientation of the SDT junction is said to be “parallel.” If the magnetization vectors of the pinned and sense layers are in opposite directions, the orientation of the SDT junction is said to be “anti-parallel.”
These two stable orientations, parallel and anti-parallel, represent logic values of ‘0’ and ‘1.’ The magnetization orientation, in turn, affects the resistance of the SDT junction. Resistance of the SDT junction is a first value if the magnetization orientation is parallel and a second value if the magnetization orientation is anti-parallel. The magnetization orientation of the SDT junction and, therefore, its logic value may be read by sensing its resistance state.
The memory cell array may be fabricated by depositing a stack of magnetic memory element layers, and patterning the stack into memory elements. Ideally size, shape and thickness of the memory elements are uniform.
In practice, however, the thickness, size and shape are not uniform. Variations in size, shape, and layer thickness result in variations in the magnetic properties of the memory elements in the MRAM array. In particular, the variations of these parameters can occur from wafer-to-wafer, but they can also occur from die-to-die and array-to-array. These variations can reduce the integrity of writing of data and may also have the undesired side effect of unselected bit erasure. As the memory elements are reduced in size, these variations and their undesired effects become more prominent, especially with respect to switching coercivity of the sense layers.
Yet it is a goal of memory manufacturers to reduce the size of the memory elements. Reducing the size increases storage density, which, in turn, reduces storage cost. Reducing the size also reduces power consumption, which is advantageous for mobile products.
SUMMARY
According to one aspect of the present invention, a magnetic tunnel junction is fabricated by forming pinned and sense layers; and re-setting a magnetization vector of at least one of the layers. Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.
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Anthony Thomas
Sharma Manish
Tran Lung
Hewlett--Packard Development Company, L.P.
Lebentritt Michael
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