Method for modifying a chip layout to minimize within-die CD...

Details Method for modifying a chip layout to minimize within-die CD... Method for modifying a chip layout to minimize within-die CD...

2005-05-24

2005-05-24

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C700S110000, C700S120000, C700S121000, C430S005000, C378S035000, C382S144000

Reexamination Certificate

active

06898781

ABSTRACT:
A method including determining a first flare convolution based on a feature density of projected structures on a substrate layout, determining a second flare convolution based on a mask for a given substrate layout, determining a system flare variation by summing the first flare convolution and the second flare convolution, and determining a critical dimension variation based on the system flare variation.

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Singh, “The importance of layout density control in semiconductor manufacturing” http://www.eda.org/edps/edp03/submissions/paperVivek2.pdf□□.

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