Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-02-01
2003-09-23
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06625802
ABSTRACT:
FIELD
The invention relates to circuit patterning and more particularly to patterning using extreme ultra-violet lithography.
BACKGROUND
Patterning is the series of steps that results in the removal of selected portions of surface layers added on a substrate such as a wafer. Patterning creates the surface parts of devices that make-up a circuit. One goal of patterning is to create in or on the wafer surface, the parts of the device or circuit in the exact dimensions (feature size) required by the circuit design and to locate the parts in their proper location on a wafer surface. Generally speaking, patterning sets the critical dimension of devices of a circuit.
Generally, patterning is accomplished through photolithography techniques. In general, photolithography is a multi-step pattern transfer process whereby a pattern contained on a reticle or photomask is transferred onto the surface of a wafer through a lithographic imaging step, including the development of a light sensitive material (e.g., photoresist) on the wafer. In general, the smallest feature printable by the imaging system is proportional to the following quantity:
λ
NA
where &lgr; is the wavelength of light used in imaging the mask onto the wafer and NA is the numerical aperture of the projection optics.
One goal of circuit designers is to reduce the feature size (the critical dimension) of devices of a circuit, i.e., reduce the smallest feature patternable. A reduction in wavelength of light used in patterning will reduce the smallest feature patternable as will an increase in the numeral aperture of the lens. Unfortunately, an increase in the numerical aperture of the lens tends to be quite expensive. Thus, the recent trend has been to reduce the wavelength. Currently, wavelengths of light used in patterning integrated circuits are 248 nanometers or less for a critical dimension on the order of 130 nm. As the critical dimension approaches 100 nanometers or less, the wavelength will be reduced to under 200 nanometers, and will eventually lie in the extreme ultraviolet (EUV) region.
In the general course of patterning, the image of a reticle or photomask is projected onto a wafer by an imaging system. Typically, the imaging system is refractive and is composed of lenses fabricated out of glass or quartz. EUV radiation, however does not pass through quartz or glass. Thus EUV imaging relies on reflective optics.
The short wavelengths used for imaging in EUV lithography raises a concern about flare. Flare is unwanted background light. It comes from locations away from the feature of interest and it reduces the printability of the image. Furthermore, variations of flare over the image cause unwanted changes in the printed size of critical features. Flare results from scattering off of imperfections on the mirror surfaces used as the optical elements of the EUV imaging system. There is a limit on how smooth the mirror surface can be, and even at the atomic level (e.g., three to four atoms), roughness in the mirror can cause significant light scattering. This light scattering leads to background illumination, called flare. This background illumination can be tolerated so long as it is not too large and is uniform across the wafer.
The flare at any location is a function of the surrounding mask layout. In general, a mask layout for a circuit design on a wafer is very complex and does not consist of a repeatable or uniform pattern. This variation in pattern layout results in non-uniform flare.
What is needed is a technique to determine a the variation of flare across the image; with this knowledge, techniques can be implemented to compensate for the non-uniformity of the flare.
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Krautschik et al., “Rigorous modeling of scattered light in EUV cameras” Microprocesses and Nanotechnology Conference, 2001 International , Oct. 31-Nov. 2, 2001, pages(s): 14.*
Singh, “The importance of layout density control in semiconductor manufacturing”www.eda.org/edps/edp03/submissions/paperVivek2.pdf.
Bjorkholm John Ernst
Leon Francisco A.
Singh Vivek K.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Liu Andrea
Smith Matthew
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