Method for modifying a C4 semiconductor device

Details Method for modifying a C4 semiconductor device Method for modifying a C4 semiconductor device

2000-02-10

2002-10-22

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S714000, C438S723000, C438S725000, C438S745000

Reexamination Certificate

active

06468917

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly to the modification of semiconductor devices.
BACKGROUND OF THE INVENTION
The modification and verification of circuit design changes is a part of the normal fabrication process of semiconductor devices, including the fabrication of controlled collapse chip connection (C4) devices.
FIGS. 1A and 1B
illustrate cross-sectional and top views of a conventional C4 device, respectively. As illustrated in
FIG. 1A
, the C4 device
100
includes a die
102
with an active region
104
on one side. The active region
104
contains the circuitry of the device
100
and is connected to a package substrate
106
via a plurality of solder bumps
108
. In the current state of the art, the size of the circuit structures in the active region
104
are in the sub-micron range. The active region
104
may be protected by a layer of polyimide (not shown). On the other side of the package substrate
106
are pins
110
which connect the C4 device to a printed circuit board (not shown). As illustrated in
FIG. 1B
, the package substrate
106
contain footprints
112
composed of solder. The locations of the footprints
112
correspond to the solder bumps
108
on the active region
104
.
When circuit modification is required before packaging, the die
102
with solder bumps
108
is removed from a whole wafer which has been sawed into single die pieces. A focused ion beam (FIB) can be used to cut and deposit metal in the desired locations. Circuit structures on semiconductor devices may be located by obtaining a scanning electron microscope (SEM) image of the top layer of the circuit, and then using the SEM image of the top layer as a reference to align a circuit layout. However, since the active region
104
is covered by a polyimide layer, the SEM image of the top layer is featureless. Thus, as illustrated in
FIG. 2
, in order to find circuit structures, first a section of the polyimide layer
114
needs to be removed by the FIB to expose a portion
116
of the top layer. The exposed portion
116
can then be used as a reference for locating the desired circuit structures. Circuit modification at the desired locations may then be performed.
However, the removal of the portion of the polyimide layer
114
using the FIB is time consuming. The FIB is also a very costly system. The use of the FIB in this time consuming manner increases the cost of device fabrication and the time of the new device introduction to the market.
Accordingly, there exists a need for an improved method for modifying a C4 device. The method should be easy to implement, and reduce the cost and increase the accuracy of the circuit modification. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method for modifying a C4 device, the device including a circuit, a polyimide layer, and a plurality of solder bumps in the active region of the C4 device. The method includes removing the polyimide layer using a plasma etch, the plasma etch comprising a mixture of oxygen and an inert gas; modifying the circuit; and cleaning the modified C4 device with a reactive flux. By mixing the oxygen with an inert gas, the oxidation of the solder bumps due to the plasma etch are reduced. Because the top layer features are now readily visible, circuit structures are more easily located, and modification can be more easily performed and with more accuracy. In the preferred embodiment, the device is then cleaned with a reactive flux, which removes any oxidation layer which has formed on the solder bumps. In this manner, circuit modification may be performed more quickly while also minimizing the oxidation of the solder bumps. The reduced oxidation of the solder bumps will help the C4 packaging process to be successful for electrical testing after focused beam ion (FIB) modification. Also, since the costly FIB process is not required to locally remove the polyimide layer for locating circuit structures, the cost of device fabrication is reduced.


REFERENCES:
patent: 5110712 (1992-05-01), Kessler et al.
patent: 5869899 (1999-02-01), Arledge et al.
patent: 5938856 (1999-08-01), Sachdev et al.
patent: 6074895 (2000-06-01), Dery et al.
patent: 6159754 (2000-12-01), Li et al.

Affiliated with

Also associated with

Rating

Method for modifying a C4 semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for modifying a C4 semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for modifying a C4 semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2934191