Method for modeling integrated circuit yield

Details Method for modeling integrated circuit yield Method for modeling integrated circuit yield

2006-03-14

2006-03-14

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07013441

ABSTRACT:
A method and system for predicting manufacturing yield for a proposed integrated circuit The method includes: in the order recited: (a) providing a multiplicity of different integrated circuit library elements in a design database, each library element linked to a corresponding normalization factor in the design database; (b) selecting library elements from the design database to include in a proposed design for the integrated circuit; (c) generating an equivalent circuit count of the proposed design based on the normalization factors and a count of each different library element included in the proposed design; and (d) calculating a predicted manufacturing yield based on the equivalent circuit count, a predicted density of manufacturing defects and an area of the proposed integrated circuit chip.

REFERENCES:
patent: 5539652 (1996-07-01), Tegethoff
patent: 6449749 (2002-09-01), Stine
patent: 6496958 (2002-12-01), Ott et al.
patent: 6738954 (2004-05-01), Allen et al.
patent: 6751519 (2004-06-01), Satya et al.
patent: 6795952 (2004-09-01), Stine et al.

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