Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Patent
1997-07-14
1998-05-12
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
438528, H01L 21425
Patent
active
057504350
ABSTRACT:
An N-Channel Metal Oxide Semiconductor Field Effect Transistor (N-MOSFET) with minimum susceptibility to the Hot Carrier Effect (HCE) and a method by which the N-MOSFET is fabricated. Formed upon a semiconductor substrate is a N-MOSFET structure including a gate oxide upon a semiconductor substrate, a gate electrode upon the gate oxide and a pair of N+ source/drain regions adjoining the gate electrode and the gate oxide. Implanted into the gate oxide regions beneath the gate electrode edges is a dose of a hardening ion. The hardening ion may be either nitrogen ion or fluorine ion. The hardening ion is implanted at an angle non-orthogonal to the plane of the semiconductor substrate through means of a large tilt angle ion implant process. Optionally, a Lightly Doped Drain (LDD) source/drain electrode structure or Double Doped Drain (DDD) source/drain electrode structure may be incorporated into the N-MOSFET structure.
REFERENCES:
patent: 5108935 (1992-04-01), Rodder
patent: 5155369 (1992-10-01), Current
patent: 5223445 (1993-06-01), Fuse
patent: 5270227 (1993-12-01), Kameyama et al.
patent: 5308780 (1994-05-01), Chou et al.
patent: 5346841 (1994-09-01), Yajima
patent: 5360749 (1994-11-01), Anjum et al.
patent: 5369297 (1994-11-01), Kusunoki et al.
patent: 5372957 (1994-12-01), Liang et al.
patent: 5496751 (1996-03-01), Wei et al.
patent: 5516707 (1996-05-01), Loh et al.
Kuroi et al., Novel NICE (Nitrogen Implantation into CMOS Gate Electrode and Source-Drain) Structure for High Reliability and High Performance 0.25 um Dual Gate CMOS, IEDM 1993, IEEE, 13.2.1-13.2.4, pp. 325-328, 1993.
Wolf et al., "Silicon Processing for the VLSI Era", vol. II, Lattice Press, 1990, pp. 361-363.
Ackerman Stephen B.
Bowers Jr. Charles L.
Chartered Semiconductor Manufacturing Company Ltd.
Gurley Lynne A.
Saile George O.
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