Method for minimizing program disturb in a memory cell

Details Method for minimizing program disturb in a memory cell Method for minimizing program disturb in a memory cell

2000-07-17

2001-04-24

Phan, Trong (Department: 2824)

Static information storage and retrieval

Floating gate

Disturbance control

C365S185290

Reexamination Certificate

active

06222761

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an improved method for erasing and writing information in an electrically alterable memory, and more particularly to a method of erasing and writing information in an electrically erasable programmable read only memory (“EEPROM”).
We have discovered a unique solution to the “program disturb” problem in memory cells such as those in current P-channel EEPROM structures. Program disturb occurs when there is a write or erase to a selected group of cells in an array, and the state or content of other, nonselected cells, which is supposed to be left unchanged, is unintentionally changed. The program disturb of such other, non-selected cells may not occur as a result of one programming cycle. The unwanted change may occur incrementally and gradually over many (even millions of) programming cycles. The program disturb problem can be quite subtle and difficult to observe, but can be severely limiting for some applications of the cell.
We use the nomenclature for electrical operations performed upon an array of memory cells in a slightly different manner than typically occurs. We use here the term “write” to refer to an operation of placing electrons onto a floating gate. We use the term “erase” to refer to an operation of removing electrons from a floating gate. The term “program” as used here refers to one cycle of cell programming, which includes a write operation and an erase operation.
This invention represents an improvement upon the structure and operation described in the following patents: U.S. Pat. No. 5,790,455, “Low Voltage Single Supply CMOS Electrically Erasable Read-Only Memory;” U.S. Pat. No. 5,986,931, “Low Voltage Single CMOS Electrically Erasable Read-Only Memory;” and in the following patent applications: U.S. patent application Ser. No. 09/262,675, and entitled “Independently Programmable Memory Segments within a PMOS Electrically Erasable Programmable Read Only Memory Array Achieved by N-well Separation and Method Therefor,” Filed Mar. 19, 1999; and U.S. Patent Application filed concurrently herewith, and entitled “Improved Programming Method for a Memory Cell”, both applications assigned to the same assignee as the present application. Based on these two patents and applications, the following summarizes the overall structure of an EEPROM memory array and the voltages applied to it during the write and erase operations.
The program disturb problem occurs because groups of cells share a number of common connections, including: a bit line, a word line, a source line, and an N-well. However, cells need to share these connections in order to make the memory array compact and to reduce the number of signal lines routed into it. So, an understanding of the structure and operation of a current memory array is useful for understanding how the disturb problem arises and how the present invention addresses this problem.
FIG. 1
is a circuit schematic diagram of a p-channel memory cell, which will be referred to as the PEEC cell (p-channel EEPROM Cell).
FIG. 2
is a schematic cross-section diagram of the PEEC cell, along the channel of the
FIG. 1
device and in a direction parallel to the bit line. By comparing
FIGS. 1 and 2
, a correspondence can be seen between the various symbolic representations of the cell components in
FIG. 1
with their physical embodiment in the cross-section of FIG.
2
. For example, the source and drain of the cell are represented by simple lines on either side of the word line in FIG.
1
and these are actually p-type diffusions in an n-well shared by many memory cells as depicted in FIG.
2
. In fact, each source and drain diffusion is actually shared by two adjacent cells. The “fragments” of poly
2
to the left and right of the poly
2
word line of the cell in the center of the diagram indicate this. In
FIG. 1
, it can be seen that there are four terminals to the cell: (1) the poly
2
word line that is shared by a row of cells, (2) the source that is connected to the metal source line, (3) the drain that is connected to the metal bit line, and (4) the N-well body that is a region of n-type silicon shared by several columns of cells. Physically, the metal bit line and source line run parallel to each other in pairs down each column of the array. Each column of cells has one bit line and one source line.
In
FIG. 2
, the cross-section is along and through the bit line so the metal line is visible in the cross-section. The metal source line and its contact to the source p+ region is not visible in
FIG. 2
because it is parallel to the bit line and out of the plane of the paper.
FIG. 1
also indicates where voltages are applied to the PEEC cell to program or read the cell information. These voltages are labeled V
BL
(the voltage on the bit line), V
NW
(the voltage on the shared N-well region), V
SRC
(the voltage on the source line), and V
WL
(the voltage on the word line).
FIG. 3
is a schematic diagram of a portion of a large memory array. An N-well region is depicted as a dashed line box surrounding a large group of memory cells. In the figure, two N-wells, labeled N-well #
0
and N-well #
1
, are shown. N-well #
0
contains eight complete columns of cells. N-well #
1
would normally also contain eight columns of cells, but only 4 columns are shown due to space limitations in the figure. Eight columns are shown as being contained in one N-well because this is the typical size of a “byte” or “word” of information. One “byte” or “word” would actually be the number of cells along the intersection of one word line with the number of columns in one N-well. Thus, one N-well contains many bytes or words, corresponding to the many word lines that cross the N-well. However, any number of columns could be contained in a single N-well (i.e. the “byte” or “word” size could be 14, 16, 32, or any number desired for the product). Also, there could be any number of N-well segments in the large array. Only two are shown because this is sufficient for the present description.
In
FIG. 3
, only the top four and last two rows of cells (word lines) are shown due to space limitations. In this figure, it is assumed that there are n+1 word lines, numbered from 0 through n. The number n could be only a few, or it could be hundreds or thousands. The schematic diagram for one PEEC cell that appears in
FIG. 1
can be seen repeated many times in the array depicted in FIG.
3
. Cells in the same column share a bit line, a source line, and the N-well (note the three parallel lines running down each column). Cells in the same row share a word line (note the single horizontal line running along each row). All cells in the array are identified individually by the notation, M
x,y
, where x=the row number and y=the column number.
At the bottom of each column, the last transistor is not a PEEC cell, but a source select transistor, denoted by the notation Q
z,y
, where z=the N-well number and y=the column number. The source select transistor is, as taught in the prior art patents, used at the bottom of each column to separate the column source lines during the erase operation. Otherwise the undesirable condition of having the programming high voltage signal shorted to ground could occur. The source select transistor must be turned on to read a cell and off during the erase part of a programming cycle. This is accomplished by the line running left to right which connects all of the source select transistor gates, and has the voltage label at its terminus, V
sel
. When the source select transistor is turned on, it connects the voltage, V
src
, which is connected to all the source select transistors to the source lines. The voltages applied to the N-wells are labeled, V
NW0
and V
NW1
. The voltages applied to the word lines are labeled, V
WL0
, V
WL1
, . . . , V
WLn
. The voltages applied to the bit lines are labeled, V
BL0
, V
BL1
, and so on. Many commercial products, such as “byte-selectable” or “full-featured” EEPROM memories, select and program only one

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