Method for minimizing ground bounce in digital circuits via time

Details Method for minimizing ground bounce in digital circuits via time Method for minimizing ground bounce in digital circuits via time

1995-09-06

1996-11-05

Hudspeth, David R.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 28, 326 86, H03K 1716

Patent

active

055721451

ABSTRACT:
A switching array is formed with a plurality of switches each having an input and an output. The switches are associated with a digital bus, such as an address or data bus, and transfer the values on their inputs to their outputs when a control signal is received. When the switches undergo a transition from a logical value of "1," which is about the supply voltage down to a logical value of "0," which is about the ground potential, the switches produce a load current which is discharged to ground. In a first embodiment, the load current is divided into two parts and discharged to ground at two different times by using switches which have two different speeds. The faster switches will discharge the load current first followed a time later by the second slower group of switches. In a second embodiment, the switches all have the same speed and the control signal is delayed to half of the switches. Thus, the switches receiving a delayed control signal will discharge a load current later than the other switches. By dividing the load current into two halves and discharging the two load currents at different times, the ground plane is better able to absorb the load current.

REFERENCES:
patent: 4587445 (1986-05-01), Kanuma
patent: 4857765 (1989-08-01), Cahill et al.
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patent: 5229657 (1993-07-01), Rackley
patent: 5319260 (1994-06-01), Wanlass
patent: 5323070 (1994-06-01), Ueda et al.

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