Method for minimizing clock skew for an integrated circuit

Details Method for minimizing clock skew for an integrated circuit Method for minimizing clock skew for an integrated circuit

2001-03-06

2003-07-15

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06594807

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to synchronizing clock pulses among layout blocks of an integrated circuit. More specifically, but without limitation thereto, the present invention relates to inserting a minimum set of delay cells between a clock driver and each circuit element to synchronize clock pulses in an integrated circuit.
An integrated circuit chip design typically includes a hierarchy of layout blocks, or hard macros (“hardmacs”). These circuit elements generally require a common clock pulse to synchronize their operation with one another. Because the wire length between a clock pulse generator and each circuit varies, the propagation delays in the wiring also vary. The clock pulses arrive at each circuit element at a different time due to the propagation delays in the wiring. This variation in propagation time of the clock pulses to each of the circuit elements is called clock skew. In high speed circuits, clock skew of 100 picoseconds may cause a malfunction in the chip.
Current methods for correcting clock skew add compensating lengths of wire to balance the propagation delays. A disadvantage of these methods is that the increased wire length increases capacitive coupling to other circuits and adds loading capacitance that may distort the clock pulse waveform.
SUMMARY OF THE INVENTION
The present invention advantageously addresses the problems above as well as other problems by providing a method for synchronizing clock pulses for an integrated circuit by a balanced clock tree with delay cells.
In one embodiment, the present invention may be characterized as a method for synchronizing clock pulses for an integrated circuit that includes the steps of (a) finding a relative delay with respect to a clock signal for a plurality of circuit elements and (b) inserting a delay cell between the clock signal and each of the plurality of circuit elements for each of the plurality of circuit elements that has a relative delay greater than a minimum delay to minimize clock skew.


REFERENCES:
patent: 5394024 (1995-02-01), Buckenmaier et al.
patent: 5557779 (1996-09-01), Minami
patent: 5578938 (1996-11-01), Kazami
patent: 5600568 (1997-02-01), Iwakura et al.
patent: 5767720 (1998-06-01), Osera et al.
patent: 5923570 (1999-07-01), Shigemoto
patent: 6266803 (2001-07-01), Scherer et al.
patent: 6425114 (2002-07-01), Chan et al.
patent: 2002/0073389 (2002-06-01), Elboim et al.

Affiliated with

Also associated with

Rating

Method for minimizing clock skew for an integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for minimizing clock skew for an integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for minimizing clock skew for an integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3063125