Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-10-11
2003-07-22
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06596635
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally in the field of semiconductor fabrication. More particularly, the present invention is in the field of metallization for semiconductor substrates.
2. Related Art
Metallization refers to the process of depositing metal on the surface of a semiconductor substrate or other layers existing on the semiconductor substrate. Of particular interest in semiconductor fabrication is “backside metallization” which refers to the process of depositing metal on the backside surface of a semiconductor substrate. Although throughout the present application reference is made to the specific example of “backside metallization” to describe the related art as well as the advances made by the present invention, it is appreciated by a person of ordinary skill in the art that the shortcomings of the related art described herein, as well as the solution provided by the present invention, apply to metallization of large areas of a semiconductor die, whether such large areas are on the backside or frontside of the die, or whether such large areas contain features such as trenches, dips, holes, tubs, ridges, mesas, or are featureless and plane.
Continuing with the specific example of backside metallization, it (i.e. backside metallization) may be implemented in semiconductor fabrication to realize a number of goals including, for example, improved thermal conductivity by way of an effective outlet for heat dissipation from the die. Backside metallization is also frequently used for reducing inductance, as well as other electrical advantages. As an example of backside metallization, a backside layer of gold is typically used to attach a die to its package by eutectic techniques where the layer of gold also provides the thermal and electrical advantages mentioned above.
The formation of a strong bond between a metal layer and the substrate backside surface is important for a variety of reasons. For example, a strong bond is necessary to prevent peeling of the metal layer, and in particular the backside metal layer, from the substrate during subsequent processing steps. One concern, for instance, is the backside metal layer's susceptibility to peeling during die separation, which may involve scribe-and-break steps, or during die pick. If the bond is not sufficiently strong, peeling may also occur when the die is bonded during the die attach process. Such processes subject the die to mechanical forces that can compromise the bond between the backside metal layer and the semiconductor substrate, leading to low yield and throughput, or may ultimately affect the performance and durability of the die.
The bond achieved by backside metallization techniques known in the art have proven inadequate and/or impractical, most notably when backside metallization is performed on group III-V compound semiconductors, such as gallium-arsenide, indium-phosphide, or gallium-nitride, for example. In U.S. Pat. No. 4,946,376, titled “Backside Metallization Scheme for Semiconductor Devices,” for example, a backside metallization process is disclosed wherein the backside metal layer comprises a layer of vanadium deposited over the backside of the wafer and a layer of silver disposed over the vanadium. According to this scheme, the vanadium layer acts as the adhesion layer. Another method for backside metallization is disclosed in U.S. Pat. No. 6,140,703, titled “Semiconductor Metallization Structure,” wherein a layer of titanium is used as the adhesion layer, while a nickel-vanadium layer, deposited over the adhesion layer, functions as a barrier layer.
Other known schemes use a combination of Ti/Pt/Au, Ti/Au or Ti/Ni/Au for metallization. According to the scheme, adhesion of the metal layer to the substrate surface is provided by Ti, which does not react well with group III-V compounds, and the adhesion relies primarily on oxide formation. However, oxides on group III-V compounds are poorly bonded to the substrate, and as such, this scheme results in a backside metal layer that is prone to peeling. For at least the same reason, a known scheme using Cr/Au, with Cr being the glue layer, is inadequate, since it also relies on oxide formation. Other known backside metallization methods may utilize other materials and compositions of materials, but each has its own drawbacks, and none has led to the level of reliability desired.
The need for well adhering backside metallization is magnified in instances where the backside of the semiconductor substrate includes various features, rather than being flat or featureless. For example, some manufacturers implement Through Wafer Vias (“TWV”) into their chips. TWV, which may also be referred to as “backside vias”, are vias etched from the backside of the wafer through the semiconductor substrate and other intervening layers to land on a desired metal layer or component in the chip, such as a ground pad. TWV can provide both thermal and electrical advantages, including reducing electrical resistance and inductance, and lowering thermal resistance, which permit manufacturers to produce chips having higher power efficiency on smaller die sizes. The presence of such features, including TWV, makes it more difficult to deposit the adhesion and seed layers properly for strong bonding between the backside metal layer and the backside substrate surface, consequently leading to a higher manufacturing defect rate due to, for example, peeling.
There is thus need in the art for an effective and reliable method for metallization of large areas in a semiconductor substrate and, in particular, for backside metallization of group III-V compound semiconductors and related structure.
SUMMARY OF THE INVENTION
The present invention is directed to method for metallization of a semiconductor substrate and related structure. In particular, various embodiments of the present invention overcome the need in the art for an effective and reliable method for metallization of large areas in a semiconductor substrate and, in particular, for backside metallization of group III-V compound semiconductors and related structure. Although throughout the present application reference is made to the specific example of “backside metallization” to describe the present invention, it is appreciated by a person of ordinary skill in the art that the principles of the present invention apply to metallization of large areas of a semiconductor die, whether such large areas are on the backside or frontside of the die, or whether such large areas contain features such as trenches, dips, holes, tubs, ridges, mesas, or are featureless and plane.
According to one embodiment, a nickel-vanadium (“NiV”) adhesion layer is deposited over the backside surface of a semiconductor substrate. The semiconductor substrate might comprise a group III-V compound semiconductor, such as gallium-arsenide, indium-phosphide or gallium-nitride. The NiV adhesion layer might comprise, for example, approximately 93% nickel and 7% vanadium, or generally anywhere from 100% to 80% nickel and 0% to 20% vanadium. The NiV adhesion layer can be deposited over the backside surface of the semiconductor substrate in, for example, a magnetron deposition system, and can be between approximately 30 and 2000 Angstroms thick. In certain embodiments, the backside surface of the semiconductor surface may be cleaned to remove oxides from the surface prior to deposition of the NiV adhesion layer.
After the NiV adhesion layer has been deposited, a gold seed layer is deposited over the NiV adhesion layer. As an example, the gold seed layer can be between approximately 100 and 2500 Angstroms thick. Following deposition of the gold seed layer, a second gold layer is electroplated over the gold seed layer. The second gold layer can also be deposited by other techniques known in the art. The second gold layer can be between approximately 0.5 and 25 microns thick, for example. A backside metal layer comprising an NiV adhesion layer, a gold seed layer, and a second gold layer can thus be effectively ac
Burton Richard S.
Knoedler Heather L.
Tiku Shiban K.
Farjami & Farjami LLP
Hoang Quoc
Nelms David
Skyworks Solutions Inc.
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