Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-10-07
2004-11-16
Wilczewski, M. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S626000, C438S628000, C438S631000, C438S644000, C438S645000, C438S648000
Reexamination Certificate
active
06818555
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to semiconductor processing methods including metallization processes and more particularly to metal filling of semiconductor features, including those with relatively wide opening dimensions, together with a metal etchback process including a self aligned etching mask to achieve planarization without the necessity of chemical mechanical polishing (CMP).
BACKGROUND OF THE INVENTION
Metallization interconnects are critical to the proper electronic function of semiconductor devices. Several advances in semiconductor processing have been aimed at improving signal transport speed by reducing metal interconnect resistivities and improving resistance to electromigration effects. Copper has increasingly become a metal of choice in, for example, upper levels of metallization in a multi-level semiconductor device due to its low resistivity and higher resistance to electromigration. Tungsten is still preferred for use in the lower metallization layers adjacent to the silicon substrate since it provides an effective diffusion barrier to metal diffusion from overlying metallization layers to react with the silicon substrate. Tungsten further has high resistance to electromigration and can effectively be used to fill high aspect ratio vias by chemical vapor deposition (CVD) processes.
A serious problem in tungsten plug formation according to prior art methods of using a dry etchback process to remove the tungsten metal above a feature level is that during the dry etchback etching process, relatively wide dimensioned semiconductor features exhibit anisotropic-like etching of the tungsten metal filling, leaving little or no tungsten in a major portion of the feature while leaving a portion of the tungsten covering the feature sidewalls. For example, typical tungsten feature openings are practically limited to a maximum width or diameter of the feature opening at about 1 micron with a tungsten layer about 8000 Angstroms to about 10000 Angstroms thick due to considerations of cost, deposition time, and etchback time. In addition, feature opening dimensions of greater than about 1 micron require a CMP method to planarize the surface above the feature opening following tungsten deposition since metal etchback methods tend to produce anisotropic-like etching that preferentially etches into the metal filling for larger dimensioned feature openings.
For example, referring to
FIG. 1A
, is shown a cross sectional side view of a portion a semiconductor device at a stage in manufacture showing etched openings,
12
A and
12
B, overlying a conductive areas e.g.,
14
A,
14
B which overlies a semiconducting substrate
16
A. The etched openings,
12
A and
12
B are formed in a dielectric insulating layer
16
B and an adhesion layer, also referred to as a glue layer,
18
A is blanket deposited to line the openings to improve the adhesion of subsequently deposited tungsten. A tungsten layer
18
B is then blanket deposited over the adhesion layer
18
A. According to a chemical vapor deposition (CVD) method conforming to the general outline of, for example, the relatively wider dimensioned feature,
12
A. For example, feature
12
A is a contact opening having a width dimension of about 2 microns.
Referring to
FIG. 1B
, a dry etchback process is used to etchback the tungsten layer
18
B. As is apparent in
FIG. 1B
, for example, the etching of the relatively wider dimensioned feature
12
A, experiences anisotropic etching where the center portion of the tungsten filling is removed while leaving a portion of the tungsten layer e.g.,
18
B covering the feature sidewalls. As a result, prior art dry etchback processes have not been successfully implemented to planarize relatively wide dimensioned metal filled features including tungsten filled features.
Therefore, there is a need in the semiconductor processing art to develop a method for a reliable metal etchback process to planarize metal filled semiconductor features, including tungsten filled semiconductor features.
It is therefore an object of the invention to provide a method for a reliable metal etchback process to planarize metal filled semiconductor features, including tungsten filled semiconductor features while overcoming other shortcomings of the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for a metal etchback process to form a metal filled semiconductor feature having improved planarity and electrical resistance.
In a first embodiment, the method includes providing a semiconductor wafer having a process surface including an etched opening lined with a refractory metal containing layer and having a blanket deposited metal layer substantially filling the etched opening; spin coating a spin on layer (SOL) selected from the group consisting of an organic resinous layer and a spin-on glass (SOG) layer over the metal layer; dry etching in a first etchback process to remove a first portion of the SOL layer to reveal a portion of the metal layer leaving a second portion of the SOL layer overlying the etched opening; dry etching in a second etchback process to remove the metal layer to reveal a portion of the refractory metal containing layer; and, removing the second portion of the SOL layer to form a substantially planar metal filled etched opening.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.
REFERENCES:
patent: 4775550 (1988-10-01), Chu et al.
patent: 4894351 (1990-01-01), Batty
patent: 5256248 (1993-10-01), Jun
patent: 5350486 (1994-09-01), Huang
patent: 5378318 (1995-01-01), Weling et al.
patent: 5461010 (1995-10-01), Chen et al.
patent: 5639345 (1997-06-01), Huang et al.
patent: 5753547 (1998-05-01), Ying
patent: 5792705 (1998-08-01), Wang et al.
patent: 5814186 (1998-09-01), Nguyen
patent: 5930677 (1999-07-01), Zheng et al.
patent: 5968847 (1999-10-01), Ye et al.
patent: 6008105 (1999-12-01), Ukeda et al.
patent: 6121136 (2000-09-01), Sung
patent: 6180511 (2001-01-01), Kim et al.
patent: 6218291 (2001-04-01), Yoon et al.
patent: 6265315 (2001-07-01), Lee et al.
patent: 6391781 (2002-05-01), Ozawa et al.
patent: 2000-260868 (2000-09-01), None
Liu Hung-Hsin
Tsai How-Cheng
Young Chung-Daw
Yu Ming-Kuo
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
Wilczewski M.
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