Method for memory optimization in a digital signal processor

Details Method for memory optimization in a digital signal processor Method for memory optimization in a digital signal processor

2006-01-24

2006-01-24

Tsai, Henry W. H. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S208000

Reexamination Certificate

active

06990571

ABSTRACT:
According to one embodiment, a processing element is disclosed. The processing element includes an instruction buffer, a first most often (MO) buffer coupled to the instruction buffer and an execution unit coupled to the instruction buffer and the first MO buffer. The execution unit is adaptable to execute instructions stored within the first MO buffer based upon a first predetermined profile.

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patent: 6615338 (2003-09-01), Tremblay et al.
patent: 6-237377 (1994-08-01), None

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