Method for measuring stress induced leakage current and gate...

Details Method for measuring stress induced leakage current and gate... Method for measuring stress induced leakage current and gate...

1999-11-30

2003-03-25

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S760020, C324S1540PB

Reexamination Certificate

active

06538462

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention is related to semiconductor wafer testing and more particularly to characterization of a dielectric film on a semiconductor wafer.
As is known in the art, semiconductor devices often contain dielectric films (e.g., silicon dioxide) grown/or deposited on a semiconductor substrate (e.g., silicon). In many devices dielectric films are sandwiched between a semiconductor and a conducting gate metal electrode to form a MOS capacitor. Contaminants and other defects at the semiconductor/dielectric interface can cause premature electrical breakdown of the gate dielectric, e.g., oxide, film or increase the leakage current across the dielectric, thus deteriorating performance of memory chips and other integrated circuits. For example, such defects can originate from precipitating impurities such as metals, often introduced during oxidation processing, plasma deposition or etching or other processing. The defects also can be formed by stacking faults, interface microroughness, and crystal originated particulates (COPs). The defects are commonly referred to as the gate oxide integrity defects (GOI's).
Testing of oxide integrity (or more generally dielectric integrity) and reliability is one of the most expensive and cumbersome tests performed in an integrated circuit fabrication process. Such testing requires a large number of metal-insulator-semiconductors (MIS) or metal-oxide semiconductor (MOS) test devices on the wafers, which are expensive to fabricate and consume a large amount of time to test.
One form of testing gate dielectric/oxide reliability includes measuring the stress-induced leakage current (SILC). SILC is a major concern for modern MOS memory devices. This measurement includes stressing the relatively thin gate dielectric films by inducing flow of electric current across the dielectric. In the prior art, tests required forming MOS or MIS test capacitors on the wafer. To monitor GOI defects, the stress was then applied co capacitors until electrical breakdown took place. The MOS and MIS test capacitors are expensive and time consuming to fabricate. In addition, testing until the breakdown occurs often takes a long period of time.
SUMMARY OF THE INVENTION
The present invention describes testing of the dielectric film on a semiconductor substrate wafer prior to fabrication of the conducting gate. The dielectric film is tested by depositing a positive ionic charge (i.e., by corona discharge in air) on the surface of the dielectric film and then measuring the characteristics of the electron current as electrons tunnel into the dielectric from an underlying semiconductor substrate wafer. In this method, corona stress causes large dielectric leakage without the dielectric film necessarily breaking down. This stress induced leakage current (SILC) extends to low electric fields and its magnitude provides a measure of the GOI defects (or gate dielectric integrity defects).
The present invention features a non-contacting method for characterizing a semiconductor wafer having a dielectric or more specifically an oxide layer disposed thereon. For example, the dielectric layer can be characterized for its Gate Oxide Integrity (GOI) and Stress Induced Leakage Current (SILC) characteristics. As used herein, the term “dielectric” includes but is not limited to oxides, e.g., SiO
2
, Ta
2
O
5
, Al
2
O
3
, nitrides, e.g., Si
3
N
4
, and barium strontium titanate (BST). Additionally, the term “GOI” refers to the integrity of the dielectric layer or film on the semiconductor substrate wafer.
In a general aspect of the invention, the method includes positioning a semiconductor wafer, having a dielectric layer disposed thereon, relative to a test device for applications of corona charge on the dielectric surface, and measuring the electric current across the dielectric layer after application of charge with the measurement test device spaced from the dielectric layer and the semiconductor wafer. The measurement test device can be for example, a vibrating Kelvin probe or a Monroe probe. The corona stress element of the test device may include a needle-type, a wire-type corona, or multiple needle-type and/or wire-type corona discharge electrode spaced from the dielectric layer. The positive corona charge applied to the surface of the dielectric on the semiconductor substrate stresses the dielectric layer causing a tunneling current between the semiconductor substrate and the dielectric layer. The amount of stress is controlled by the amount of corona charge, i.e., fluence (C/cm
2
) , deposited on the dielectric layer. For extra-low fluence, typically ≦2×10
−6
C/cm
2
, for a SiO
2
film on silicon, the method provides data on the initial tunneling characteristic and provides a means for measuring the electrical dielectric thickness T
ox
and the dielectric capacitance C
ox
, where C
ox
=∈
o
∈
ox
/T
ox
and ∈
o
is the permittivity in vacuum and ∈
ox
is the dielectric constant of dielectric layer. For high fluence, typically of about 10
−5
C/cm
2
or higher, the sequence produces data on corona stress induced leakage current, i.e., the sequence produces a tunneling current, and provides a means for measuring the gate oxide integrity. The specific low and high fluence values may be different for dielectric layers other than SiO
2
and semiconductor substrates other than silicon. In general, a high amount of stress, i.e., fluence, is applied to the dielectric layer to induce a tunnelling current at about room temperature.
The measurement test device being spaced from the dielectric layer, advantageously provides a non-contacting approach for characterizing the wafer. Because the measurement test device does not contact the wafer, the approach is non-destructive so that, in many cases, tested semiconductor substrate wafers can be reused. The method also does not require test structure preparation thereby reducing the cost of testing. The method is also very fast and suitable for mapping the entire wafer surface and providing an advantage of rapid feedback of test results to manufacturing.
In another aspect, the invention features a method of characterizing dielectric layer disposed on a semiconductor wafer. The method includes positioning the semiconductor wafer relative to a test device and measuring, with the test device, the stress induced leakage current characteristic across the dielectric layer on the semiconductor wafer with the test device spaced from the dielectric layer and the semiconductor wafer. The stress induced leakage current characteristic is a current density across the dielectric versus a dielectric field for a specific fluence of stress on the dielectric layer.
Embodiments of this aspect of the invention can include one or more of the following. Measuring the stress induced leakage current includes using the measurement test device to apply a charge to the dielectric layer of the semiconductor wafer at a level sufficient to stress the dielectric layer by causing a tunneling current flow across the dielectric, and measuring a current-voltage (I-V) characteristic after stressing the dielectric layer. The current, I, is the electric current density flowing across the dielectric and the voltage, V, is the dielectric voltage, i.e., the voltage drop across the dielectric. The dielectric layer of the semiconductor wafer is illuminated while measuring the stress induced leakage current, e.g., while measuring the current-voltage characteristic, to reduce the surface barrier contribution to the stress induced leakage current. The dielectric surface of the semiconductor wafer is also illuminated while applying the charge to the dielectric layer to further reduce the surface barrier contribution to the stress induced leakage current during subsequent measurement. The charge is applied to the dielectric layer of the semiconductor wafer with a corona stress element. Measuring the current-voltage characteristic includes measuring a surface potential difference between a probe and the dielectric layer

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