Method for measuring parasitic components of a field effect tran

Details Method for measuring parasitic components of a field effect tran Method for measuring parasitic components of a field effect tran

1996-02-12

1997-08-19

Chaudhari, Chandra

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

H01L 2166

Patent

active

056588046

ABSTRACT:
A field effect transistor for actual use and a pseudo field effect transistor are formed on a semiconductor substrate. The pseudo field effect transistor includes a source electrode, a drain electrode and a gate electrode, each being similar in shape to the field effect transistor for actual use except that it is formed without an active layer. Since the pseudo field effect transistor does not include any active layer, it becomes possible to measure only the transistor's parasitic components which are inherent to the shape of devices, such as electrodes, lead-out electrodes (pads) and lead-out conductor patterns. By comparing the characteristics (e.g., S parameter) of both the actual and pseudo field effect transistors, the characteristics of the intrinsic transistor region can be analyzed.

REFERENCES:
patent: 4961053 (1990-10-01), Krug
patent: 4962461 (1990-10-01), Meyer et al.
patent: 5320975 (1994-06-01), Cederbaum et al.

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