Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2001-01-31
2003-02-04
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C438S018000, C438S585000
Reexamination Certificate
active
06514778
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for measuring an effective gate channel length, and more particularly relates to a method for measuring an effective channel length during the application of a capacitance-voltage (C-V) method.
2. Description of the Prior Art
Channel length is a key parameter in CMOS technology used for performance projection (circuit models), short-channel design, and process monitoring. It usually differs from the gate length by an amount depending on the gate lithography and the etch bias, as well as on the lateral source/drain diffusion.
In general, channel length is determined by using an I-V (current-voltage) method, which is determined from a series of linear (low-drain-bias) I-V curves of devices with different mask lengths. The channel lengths of MOSFET are becoming increasingly difficult to measure in the deep sub-micron region due to strong variation of mobility with gate voltage, more pronounced effects of graded source/drain doping profiles, and linewidth-dependent lithography bias near the optical resolution limit.
However, the general I-V method is derived for long-channel devices and is not strictly valid for short-channel devices, so an improved channel-length extraction algorithm, called the shift-and-ratio (S&R) method, is formed. The S&R method is complicated and can not calculate the length of the gate etch bias (L
pb
) and the length of the gate to drain overlap (L
overlap
).
Accordingly, it is obvious that the conventional method for measuring the channel length is defective and then an easy and mendable method is instantly required, especially in the scaling down of devices for measuring an effective gate channel length, a gate etch bias length, and a gate-to-drain overlap length.
SUMMARY OF THE INVENTION
An object of the invention is to use a C-V method to measure an effective gate channel length in a device.
Another object of the invention is to use a C-V method more accurately to measure a gate-to-drain overlap length and a gate etch bias length in a device.
In order to achieve the previous objects of the invention, the method of the present invention comprises the following essential steps. First, a first device is provided with a source/drain and a gate mounted on a substrate. The gate of the first device is in a predetermined length L
1
, a predetermined width W
1
, and a predetermined height H
1
, wherein the predetermined width being orthogonal to the predetermined length of the gate. Next, a negative fixed voltage is applied to the gate of the first device and then a first capacitance between the gate and the source/drain of the first device is measured at the negative fixed voltage. Thereafter, a positive fixed voltage is applied to the gate of the first device and then a second capacitance between the gate and the source/drain of the first device is measured at the positive fixed voltage. Then, a gate-to-drain overlap length of the first device is determined using the measured first capacitance. Next, a gate etch bias length of the first device is determined using the measured second capacitance. Last, the effective channel length is calculated from the gate-to-drain overlap length and the gate etch bias length.
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Olsson J. et al., “A Capacitance-Voltage Measurement Method for DMOS Transistor Channel Length Extraction”, IEEE 1999 Int. Conf. on Microelectronics Test Structures, vol. 12, Mar. 1999, pp. 135-140.*
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Hong Gary
Huang Heng-Seng
Lee Yue-Shiun
Lin Shyh-Jye
Estrada Michelle
Fahmy Wael
Frazer & Murphy LLP
Powell Goldstein
United Microelectronics Corp.
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