Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-10-17
2003-12-02
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C700S110000, C700S120000, C700S121000, C430S005000, C378S035000, C382S144000
Reexamination Certificate
active
06658641
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for mask data verification in order to verify whether mask pattern data used in a manufacturing process of semiconductor devices, etc. is proper and a computer readable record medium recording the verification program
2. Description of the Related Art
When preparing mask patterns for manufacturing semiconductor devices, for the purpose of improving a margin of accuracy of wafer patterning, etc., correction processes accompanied by changes in the shapes of patterns, which are typified by the optical proximity effect corrections, have been used with growing frequency.
Among the correction processes, for example, in a case of a rule-based one-dimensional optical proximity effect correction (hereinafter referred to as OPC), there is a method to carry out a correction process as shown in
FIG. 1
by providing, for example, correction conditions shown in Table 1.
TABLE 1
Space width to
Line width to
be corrected
be corrected
a
b
c
. . .
A
&agr;
&bgr;
&ggr;
. . .
B
&dgr;
&egr;
&zgr;
. . .
C
&eegr;
&thgr;
&igr;
. . .
.
.
.
.
.
.
.
.
.
.
.
.
In the case of an example shown in Table 1 and
FIG. 1
, for each of the line widths of a mask pattern to be corrected, its correction amount is determined by a relationship with a distance to an adjacent pattern. In a mask pattern P
1
shown in
FIG. 1
, the line width is B, and a distance to an adjacent pattern P
2
is a, so &dgr; is obtained from the correction amounts shown in Table 1. As a result, the line width B of the mask pattern P
1
to be corrected is extended by a portion of &dgr;.
Thus, operations to determine the correction amount of the mask pattern and to carry out the correction are generally implemented by software on a computing apparatus.
In a process of calculating the correction amount by the software, when the correction process is not properly carried out due to some reason such as a sporadic error of the computing apparatus (memory error, etc.) and a calculation error based on an algorithm, an abnormal mask pattern is prepared so as to lead a significant problem in the manufacture of the semiconductor devices, etc. It is, therefore, required to verify whether the mask pattern is properly corrected.
However, such correction process of the mask pattern involves a change in the shape of the pattern, so it is difficult to easily verify whether the correction process is properly carried out.
Various techniques for the mask pattern verification have been previously disclosed.
For example, there is a method for verification that several check points are set on a pattern, and lengths at the check points are artificially measured by some means. In the method, when measured results are properly complied with the correction conditions, it is considered that the whole pattern is proper. However, this verification method is effective to detect a problem which affects the whole pattern, such as a mistake in the correction conditions, but other problems cannot be verified unless otherwise a problem at any of the check points accidentally occurs.
Also, as disclosed in the Japanese laid-open patent publication No. Hei. 11-174659, there is a method for verification to verify whether there is a change in a pattern which exceeds the maximum correction amount shown in a correction table which is used. The method can be implemented on both a pattern to be corrected and a corrected pattern by relatively simple graphic computations, though the method cannot verify in a case where the abnormality of the pattern resulting from an arising problem does not exceed the maximum correction amount.
Further, as disclosed in the Japanese laid-open patent publication No. Hei. 11-184064 and Hei. 11-282151, there are methods to verify by using a simulation whether the corrected result of a pattern is resolved without any trouble in a lithography process. However, the methods are to assure that the corrected result of the pattern cause no trouble in the lithography process, but not to assure the corrected mask pattern is a designed one. Also, there is a problem that the verification by using the simulation requires enormous amounts of time.
SUMMARY OF THE INVENTION
The present invention has been achieved to overcome such problems. A method for mask data verification according to the invention comprises the steps of preparing corrected mask data by each of a plurality of programs which has a different algorithm for the mask data, comparing each of the corrected mask data which is prepared in the previous step, and as a result of the comparison, if there is a difference among the corrected mask data, extracting an error which causes a problem as mask data from the difference.
The method for mask data verification further comprises the steps of preparing corrected mask data by each of a plurality of programs which has a different algorithm for the mask data, comparing each of the corrected mask data which is prepared in the previous step, and as a result of the comparison, if there are a plurality of differences among the corrected mask data, eliminating errors which cause no trouble as mask data from the differences and extracting errors which cause trouble as mask data from the remaining differences.
In this invention, in order to carry out corrections to the mask data based on predetermined conditions, corrected mask data is prepared by each of the plurality of programs which has a different algorithm. Although each of the programs has a different algorithm, its purpose is the same, so if the same correction conditions are used, each of the programs outputs an identical corrected mask data with one another. Therefore, as a result of comparing each of the corrected mask data which are prepared by the programs, if there are differences, errors which cause problems as mask data are extracted from the differences so that the verification of the mask data can be properly carried out.
Other and further objects, features and advantages of the invention will appear more fully from the following description.
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Allan et al., “Critical Area Extraction for Soft Fault Estimation”, IEEE Transactions on Semiconductor Manufacturing, vol. 11, N 1, Feb. 1998, pp. 146-154.*
Chen et al., “Analysis of the Impact of Proximity Correction Algorithms on Circuit Performance”, IEEE Transactions on Semiconductor Manufacturing, vol. 12, No. 3, Aug. 1999, pp. 313-322.
Ashida Isao
Ogawa Kazuhisa
Depke Robert J.
Holland & Knight LLC
Kik Phallaka
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