Method for mapping logic design memory into physical memory...

Details Method for mapping logic design memory into physical memory... Method for mapping logic design memory into physical memory...

2008-05-06

2008-05-06

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

11069887

ABSTRACT:
A method is provided for mapping logic design memory into physical memory devices of a programmable logic device. User constraints and physical constraints may be taken into account in generating the mapping solution. Functional block layout on the programmable logic device may be taken into account when generating the mapping solution. Multiple types of physical memory types may be considered and logic design memory may be mapped to those types of physical memory devices that are determined to be the most appropriate. A mapping solution may be optimized using, for example, simulated annealing.

REFERENCES:
patent: 5819065 (1998-10-01), Chilton et al.
patent: 6209123 (2001-03-01), Maziasz et al.
patent: 6480954 (2002-11-01), Trimberger et al.
patent: 6520559 (2003-02-01), Steffens et al.
patent: 6636935 (2003-10-01), Ware et al.
patent: 6703862 (2004-03-01), Bilski
patent: 6779169 (2004-08-01), Singh et al.
patent: 6871328 (2005-03-01), Fung et al.

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