Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...
Patent
1997-12-19
2000-08-15
Fetting, Anton W.
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
707205, 707202, 711113, 711 6, 711 4, 711114, G06F 1730
Patent
active
061051039
ABSTRACT:
A paged addressing method and associated apparatus for dynamically addressed disk storage subsystem. The present invention stores the logical to physical address map in the disk array. The logical to physical address map is divided into useful sized portions. The logical to physical address map portions containing the most recently used logical to physical address information are retained in cache. Paging techniques are used to swap the logical to physical address map portions from disk to cache when a host disk access requires a logical address not currently within the mapping information in local memory (e.g., cache). The present invention keeps track of the most recently used logical to physical address map portions in cache by defining a cache map. Furthermore, a directory resides in cache that keeps track of the physical address for each logical to physical address map portion. The present invention reduces memory requirements, because the memory map of the disk array is not stored within cache. Instead, information is demand-fetched as required. The present invention also provides for quick recovery of the logical to physical address map directory in cache in response to a cache failure during restart procedures.
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Courtright, II William V.
Delaney William P.
Fetting Anton W.
LSI Logic Corporation
Robinson Greta L.
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