Method for manufacturing wafer level chip scale package...

Details Method for manufacturing wafer level chip scale package... Method for manufacturing wafer level chip scale package...

2007-09-04

2007-09-04

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Reexamination Certificate

active

11245962

ABSTRACT:
The present invention provides a method for manufacturing a wafer level chip scale package using a redistribution substrate, which has patterned bump pairs connected by redistribution lines and formed on a transparent insulating substrate. The redistribution substrate is produced separately from a wafer and then bonded to the wafer. One part of each bump pair is in contact with a chip pad on the active surface of the wafer, and the other part coincides with one of holes formed in the wafer. Conductive lines are formed in the holes and on the non-active surface of the wafer. External connection terminals are formed on the conductive lines at the non-active surface.

REFERENCES:
patent: 2003/0113979 (2003-06-01), Bieck et al.
patent: 2005/0059188 (2005-03-01), Bolken et al.
patent: 2005/0104179 (2005-05-01), Zilber et al.

Affiliated with

Also associated with

Rating

Method for manufacturing wafer level chip scale package... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing wafer level chip scale package..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing wafer level chip scale package... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3770599