Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-04-18
2006-04-18
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S241000
Reexamination Certificate
active
07030012
ABSTRACT:
An integrated circuit device including at least one semiconductor memory array region and logic circuits including a support region is formed by the following steps. Form a sacrificial polysilicon layer over the array region. Form a blanket gate oxide layer over the device. Form a thick deposit of polysilicon in both the array region where word lines are located and in the support region where the logic circuits are located. Remove the thick polysilicon layer, the gate oxide layer and the sacrificial polysilicon layer only in the array region. Then deposit a thin polysilicon layer in both the array region and support regions. Next deposit a metallic conductor coating including at least an elemental metal layer portion over the thin polysilicon layer. Then form word lines and sate electrodes in the array region and support region respectively.
REFERENCES:
patent: 5843821 (1998-12-01), Tseng
patent: 6074908 (2000-06-01), Huang
patent: 6200834 (2001-03-01), Bronner et al.
patent: 6326260 (2001-12-01), Divakaruni et al.
patent: 6346734 (2002-02-01), Divakaruni et al.
patent: 6475893 (2002-11-01), Giewont et al.
patent: 6541810 (2003-04-01), Divakaruni et al.
patent: 6610573 (2003-08-01), Weis
patent: 6620676 (2003-09-01), Malik et al.
patent: 6620677 (2003-09-01), Hummler
patent: 2002/0196651 (2002-12-01), Weis
Divakaruni et al. “Gate Prespacers for High Density DRAMS” International Symposium on VLSI Technology Systems and Applications, Taipei, Taiwan (Jun. 8-10, 1999).
Akatsu et al., “A Highly Manufacturable 110nm DRAM Technology with 8F2 Vertical Transistor Cellfor IGb and Beyond”; Symposium on VLSI Technology; pp 52-53 (2002).
Divakaruni Ramachandra
Gluschenkov Oleg
Kwon Oh-Jung
Malik Rajeev
Dang Phuc T.
Jones Graham S.
Schnurmann H. Daniel
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