Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-03-25
2003-09-09
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S592000, C438S595000
Reexamination Certificate
active
06617229
ABSTRACT:
BACKGROUND OF THE INVENTION
This application relies for priority upon Korean Patent Application No. 2001-16310 filed on Mar. 28, 2001, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to a method for manufacturing a transistor of a double spacer structure, and more particularly, to a method for manufacturing a transistor of a double spacer structure in which an impurity ion is injected into a local portion of a lightly doped drain (LDD) region to form a local LDD region so as to prevent short channel effect and improve current characteristic of the transistor.
2. Background of the Related Art
A conventional art method for manufacturing a transistor of a double spacer structure will be described with reference to
FIGS. 1A
to
1
C.
As shown in
FIG. 1A
, a first oxide film, a polysilicon layer
15
a
, a metal layer
15
b
, a first nitride film
17
as a hard mask layer, and a photoresist film are sequentially formed on a semiconductor substrate
11
.
The photoresist film is selectively exposed and developed to remain in a region where a gate electrode will be formed.
Then, the first nitride film
17
, the metal layer
15
b
, the polysilicon layer
15
a
, and the first oxide film are etched using the selectively exposed and developed photoresist film as a mask. The photoresist film is then removed, thereby forming a gate oxide film
13
and a gate electrode
15
having a stack structure of the polysilicon layer
15
a
and the metal layer
15
b.
As shown in
FIG. 1B
, a second nitride film
19
that serves as a gate passivation film is formed on an entire surface including the gate electrode
15
.
An LDD region
21
is formed by an ion injection process and a drive-in process using the gate electrode
15
as a mask.
Subsequently, a pocket impurity ion region
23
is formed by a tilt ion injection process and a drive-in process using the gate electrode
15
as a mask.
As shown in
FIG. 1C
, a second oxide film and a third nitride film are sequentially formed on the entire surface. The third nitride film and the second oxide film are then etched back, so that a second oxide film spacer
25
and a third nitride film spacer
27
are formed at both sides of the gate electrode
15
.
Source and drain regions
29
are formed by an ion injection process and a drive-in process into the entire surface using the gate electrode
15
, the second oxide film spacer
25
, and the third nitride film spacer
27
as masks.
The conventional method for manufacturing a transistor of a double spacer structure has several problems.
During the ion injection processes of the source and drain regions and the LDD region, if energy and dose for ion injection increase in order to improve current characteristic of the transistor, short channel effect increases.
Furthermore, if the ion injection process of the pocket impurity ion region is performed to prevent the short channel effect, the current characteristic of the transistor, such as punch through, is deteriorated.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for manufacturing a transistor of a double spacer structure that substantially overcomes one or more problems due to limitations and disadvantages of the prior art.
An object of the present invention is to provide to a method for manufacturing a transistor of a double spacer structure in which a local LDD region is formed by forming a transistor including a gate electrode, an oxide film spacer and a nitride film spacer sequentially formed, dry etching the oxide film spacer using the nitride film spacer as a mask, and injecting an impurity ion into an LDD region of a portion where the oxide film spacer is etched, thereby preventing short channel effect from occurring and improving current characteristic of the transistor.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a method for manufacturing a transistor of a double spacer structure according to the present invention includes the steps of: forming a gate electrode on a semiconductor substrate; forming a gate passivation film on an entire surface; forming an LDD region and a pocket impurity ion region in a surface of the semiconductor substrate at both sides of the gate electrode; sequentially forming a first insulating film and a second insulating film on the gate passivation film, the first insulating film having different etching selectivity from that of the gate passivation film and the second insulating film; anisotropically etching the first insulating film and the second insulating film to form a double spacer structure of a first insulating film spacer and a second insulating film spacer; forming source and drain regions in a surface of the semiconductor substrate at both sides of the gate electrode including the double spacer structure; dry etching the first insulating film spacer to expose the gate passivation film between the gate electrode and the second insulating film spacer; and forming a local LDD region in the LDD region between the gate electrode and the second insulating film spacer.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5824588 (1998-10-01), Liu
patent: 5925914 (1999-07-01), Jiang et al.
patent: 5929483 (1999-07-01), Kim et al.
patent: 6020242 (2000-02-01), Tsai et al.
patent: 6207519 (2001-03-01), Kim et al.
patent: 6329279 (2001-12-01), Lee
patent: 6350665 (2002-02-01), Jin et al.
HYnix Smeiconductor Inc.
Lindsay Jr. Walter L.
Niebling John F.
Pillsbury & Winthrop LLP
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