Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2002-01-03
2003-12-30
Coleman, William David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S166000, C257S347000
Reexamination Certificate
active
06670224
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of fabricating transistors, and especially to a method of fabricating self-aligned and having low serial impedance thin film transistors.
BACKGROUND OF THE INVENTION
Recently, the requirements of lower power consumption and lighter weight have driven the rapid progress of optical technology. Liquid crystal displays (LCD) have been widely applied in electrical products, such as digital watches, calculators, etc. for a long time. Moreover, with the advance of techniques for manufacture and design, thin film transistors-liquid crystal display (TFT-LCD) have been introduced into portable computers, personal digital assistants, color televisions, and replaced gradually the kinescopes that are used for conventional displays.
Thin film transistor-liquid crystal displays (TFT-LCD) are one of various popular merchandises in the LCD field and have received much attention. In general, the TFT-LCD comprises a bottom plate on which are formed thin film transistors and pixel electrodes, and a top plate on which are constructed color filters. The liquid crystal molecules fill the space between the top plate and the bottom plate. In the operation, a signal voltage is applied to the TFT that is the switching element of each unit pixel. The TFT receives the signal voltage and turns on so that data voltage carrying image information can be applied to the corresponding pixel electrode and the liquid crystal via the TFT. When the data voltage is applied to the TFT, the arrangement of the liquid crystal molecules is changed, thereby changing the optical properties and displaying the image.
A reduction of photolithography processes in manufacturing TFT devices is necessary to decrease the process cycle time and cost. Namely, it is better to reduce the number of photomasks used in forming TFT devices. According to the prior art of manufacturing the TFT device for a TFT-LCD, two or more photomasks are needed to define the active area and gate electrode. This increases not only the process cycle time and cost required manufacture the TFT device but also the opportunity for misalignment between the active area and gate electrode.
On the other hand, it is necessary for manufacturing TFT devices to have the lower serial impedance for reducing the power loss among the source/gate/drain electrode. The conventional method for reducing the impedance is to form a salicide layer over the source/gate/drain electrode. In this process a metal layer is deposited over the source/gate/drain electrode and then a thermal process is performed to make the silicon portion of the source/gate/drain electrode react with the metal. However, a temperature of over 500° C. is required to manufacture low impedance salicide. This kind of process temperature breaks the glass substrate.
SUMMARY OF THE INVENTION
A higher number of photomasks used in manufacturing TFT requires more process cycle time and cost. The risk of misalignment also increases. Therefore, the main purpose of the present invention is to provide a method for manufacturing a self-aligned TFT-LCD apparatus. This present invention performs a back-side exposure using the active area as a mask to form the gate electrode. Only one photomask is needed to manufacture a TFT apparatus. Therefore, the present invention method may reduce costs and eliminate the misalignment risk.
The second objective of the present invention is to provide a Si-Ge layer to react with the metal layer deposited thereon for subsequent formation of a Ge-salicide having a low impedance. This kind of method may reduce the reaction temperature and resolve the high serial impedance problem.
In accordance with the foregoing purpose, the present invention discloses a manufacturing method of a TFT apparatus having low impedance. This method uses a back-side exposure process that only needs one photomask to form a TFT apparatus. On the other hand, a Si-Ge layer is deposited over the gate electrode to react with the metal deposited thereon for subsequently forming a Ge-salicide layer. The required temperature of forming a Ge-salicide layer and the impedance of the Ge-salicide layer in accordance the present invention are both lower than the salicide layer formed by the conventional method.
The method of forming a thin film transistor comprises the following steps. Firstly, a buffer layer and a amorphous thin film are formed on an insulating substrate. Then, a thermal process is performed to transfer the amorphous thin film to the polycrystalline thin film and define an active area on the polycrystalline thin film. Next, an insulating layer, an amorphous silicon layer, an amorphous silicon germanium layer and a photoresist layer are sequentially deposited on said buffer layer and said active area. The insulating layer serves as a gate dielectric layer and the amorphous silicon layer and the amorphous silicon germanium layer serves as a gate electrode. Then, a light is projected onto the back side to pattern the photoresist layer using the active area as a mask and etch the insulating layer, the amorphous silicon germanium layer and the amorphous silicon layer to form the gate electrode and gate dielectric while using the photoresist pattern as a mask. Next, ions are implanted into the active area to form a source/drain region while using the gate electrode as a mask. Then, a conductive layer is formed on the surface and a thermal process is performed to make said conductive layer react with said gate electrode and said source/drain region to form a low impedance Ge-salicide. Finally, un-reacted conductive layer is removed.
An amorphous silicon germanium layer is not deposited on the buffer layer in another embodiment of the present invention. Ge ions are implanted into the amorphous silicon layer to provide the Ge component to react with the conductive layer.
REFERENCES:
patent: 5753541 (1998-05-01), Shimizu
patent: 6410368 (2002-06-01), Kawasaki et al.
patent: 2002/0066931 (2002-06-01), Tamura et al.
Chang Ting-Kuo
Chen Pi-Fu
Dai Yuan-Tung
Kang Yu-Ming
Lee Chi-shen
Coleman William David
Industrial Technology Research Institute
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