Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-06-30
2001-05-29
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S151000, C438S479000
Reexamination Certificate
active
06238956
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a thin film transistor (TFT) and a method for manufacturing the same suitable for improving device characteristics by using a self-align technology.
2. Discussion of the Related Art
Instead of a CMOS load transistor or a load resistor, a TFT is used in an SRAM of over a 16M class or a 4M class. It is used as a switching device for switching picture data signals in each pixel region in an LCD.
Since a PMOS TFT is used as a load transistor in an SRAM cell, off-current of the load transistor is reduced and on-current is increased. Thus, power consumption of an SRAM cell is reduced and memory characteristic is enhanced, thereby proving an SRAM cell having a high quality. An offset region of a TFT is an important factor to stabilize an SRAM cell. It is significantly important how precisely offset regions are formed during its process.
A background art TFT and a method for manufacturing the same will be described with reference to the accompanying drawings.
FIG. 1
is a cross-sectional view showing a structure of a TFT, which includes an insulating layer
21
, first and second gate electrode
22
a
and
22
b
formed on the insulating layer
21
to be spaced apart from each other, a source electrode S overlapping an edge portion of the first gate electrode
22
a
, a drain electrode D connected to the second gate electrode
22
b
through a contact hole and spaced apart from the first gate electrode
22
a
, and a metal layer
27
connected to the source electrode S and the second gate electrode
22
b
. In this case, a polysilicon layer used as a channel region and an offset region is between the source electrode S and the drain electrode D. The second gate electrode
22
b
is used as a drain.
FIGS. 2A
to
2
F are cross-sectional views showing process steps of a background art method for fabricating the above-described TFT.
Referring to
FIG. 2A
, a polysilicon layer is formed on an insulating layer
21
and selectively removed to form first and second gate electrodes
22
a
and
22
b
.
Referring to
FIG. 2B
, a gate insulating film
23
is deposited on the insulating layer
21
including the first and second gate electrodes
22
a
and
22
b
.
Referring to
FIG. 2C
, a predetermined area of the gate insulating film
23
on the second gate electrode
22
b
is removed so that the surface of the second gate electrode
22
b
is exposed.
Referring to
FIG. 2D
, a polysilicon layer
24
for source and drain electrodes is formed and then an ion-injecting process for adjusting threshold voltage is performed.
Referring to
FIG. 2E
, a photoresist film is coated on the entire surface and patterned to form a mask pattern
25
. An ion-injecting process is performed by using the mask pattern
25
to form source and drain regions S and D.
Referring to
FIG. 2F
, an interlayer insulating film
26
is deposited, and the interlayer insulating layer
26
and the gate insulating film
23
are patterned to expose predetermined areas of the second gate electrode
22
b
and the source electrode S. Metal layers
27
are formed. At this time, the source region S partially overlaps the first gate electrode
22
a. The drain region D is formed spaced apart from the first gate electrode
22
a
. A channel region I and an offset region II are all formed between the source and drain regions S and D.
The background art TFT and the method for manufacturing the same have the following problems.
A photo mask process is required for forming an offset region and misalignment of photoresist changes channel region and offset region. This change of channel region and offset region deteriorates device reliability and the stability of cells an SRAM.
SUMMARY OF THE INVENTION
Therefore, the present invention is directed to a TFT and a method for manufacturing the same that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the invention is to provide a TFT and a method for manufacturing the same in which a self-align method is used to form offset region and channel region so as to minimize the change of I-V characteristic, and a gate of an inverse-T type structure is adopted to increase on-current.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the TFT includes a substrate; a gate electrode having first and second sides on the substrate; a first conductive layer pattern formed on the substrate, wherein between the first conductive layer pattern and the first side of the gate electrode is a sidewall spacer; a second conductive layer pattern formed on the substrate to be connected to the first conductive layer pattern; a gate insulating layer formed on the gate electrode; an active layer formed on the gate insulating layer, the sidewall spacer, the first conductive layer pattern, and the substrate; a source region formed in the active layer at the second side of the gate electrode; and a drain region formed on the active layer on the first conductive layer pattern.
In another aspect of the present invention, a method for manufacturing a TFT includes the steps of successively forming a first conductive layer, a first insulating layer, and a second conductive layer on a substrate; patterning the first conductive layer, the first insulating layer, and the second conductive layer to form a gate electrode having first and second sides and a first conductive layer pattern; forming a sidewall spacer on the first side of the first gate facing the first conductive layer pattern; forming a second conductive layer pattern between the sidewall spacer and the first conductive layer pattern; forming an active layer on the first insulating layer on the gate electrode, the sidewall spacer, the second conductive layer, and the substrate; and source and drain regions formed in the active layer at the second side and in the active layer on the second conductive layer, respectively.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed
REFERENCES:
patent: 5179033 (1993-01-01), Adan
patent: 5198379 (1993-03-01), Adan
patent: 5286663 (1994-02-01), Manning
patent: 5438540 (1995-08-01), Kim
patent: 5543635 (1996-08-01), Nguyen et al.
patent: 5648662 (1997-07-01), Zhang et al.
patent: 5723878 (1998-03-01), Yunai
patent: 5818070 (1998-10-01), Yamasaki et al.
Ikeda et al. (1990) Int'l Electron Devices meeting, Dec. 9-12, 1990, A Polysilicon Transistor Technology for Large Capacity SRAMs, pp. 18. 1.1-18. 1.4.
Chaudhuri Olik
Hyundai Electronics Industries Co,. Ltd.
Pham Hoai
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