Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-05-09
2004-03-30
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S303000, C438S595000
Reexamination Certificate
active
06713372
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the invention relates to a synchronous dynamic random access memory (SDRAM) capable of decreasing a leakage current generated from a cell transistor, without an additional process.
2. Brief Description of Related Technology
FIG. 1
is a cross-sectional view illustrating a conventional method for manufacturing synchronous dynamic random access memory (SDRAM).
Referring to
FIG. 1
, in a semiconductor substrate
10
, an active region is defined by a field oxide layer
12
and a well is formed. A gate insulating layer
14
is formed on the semiconductor substrate
10
and a polysilicon layer
16
and a metal layer
18
containing tungsten are successively formed on the gate insulating layer
14
, as gate materials. The metal layer
18
is a stacked layer (W/W×N) of a tungsten layer and a tungsten nitride layer.
After the formation of the metal layer
18
, an insulating layer
20
for a hard mask is formed on the metal layer
18
, and a gate G is formed by etching the metal layer
18
, the polysilicon layer
16
and the gate insulating layer
14
using the insulating layer
20
as a mask.
Subsequently, using a selective oxidation, an oxide layer
22
is formed on a surface of the semiconductor substrate
10
and on sidewalls of the polysilicon layer at a thickness of 20 Å, and a first nitride layer is deposited on a resulting structure at a thickness of 50 Å. Thereafter, first nitride layer spacers
24
are formed on sidewalls of the metal layer, the oxide layer
22
and the insulating layer
20
by blanket etching the first nitride layer, thereby to expose a portion of the surface of a semiconductor substrate
10
. The first nitride layer spacers
24
prevent blowup of the metal layer
18
generated by an oxidation in a post thermal treatment.
Next, dopants are injected into the semiconductor substrate
10
exposed at both sides of the first nitride layer spacer
24
and a source/drain regions
26
are formed by carrying out the rapid thermal process (RTP) to activate the injected dopants at a temperature of about 1000° C. for about 10 seconds in a N
2
atmosphere. Then, a second nitride spacer
28
is formed on a resulting substrate at a thickness of about 150 Å. The second nitride layer spacer
28
functions as an etching stopper when forming a contact hole for a cell contact. Deep source drains
30
, which are deeper than the source drain regions
26
, are formed by injecting dopants into the semiconductor substrate
10
exposed at both sides of the second nitride layer spacer
28
. Cell contacts
32
with deep source/drain regions
26
are formed by carrying out a polysilicon plug formation process.
However, as shown in a circle “A” of
FIG. 1
, in the above-mentioned conventional SDRAM, the semiconductor substrate
10
undergoes a stress because of the second nitride layer spacer
28
, which is directly in contact with the semiconductor substrate
10
and the stress results in defects, etc. Accordingly, a leakage current and a gate induced drain leakage current (GIDL), etc., are increased in a cell transistor, thereby to deteriorate refresh characteristic of the SDRAMs.
SUMMARY OF THE INVENTION
It would be desirable to provide a method of manufacturing synchronous dynamic random access memory (SDRAM) capable of decreasing a leakage current generated in a cell transistor, which is caused by a nitride layer stress.
Accordingly, disclosed herein is a method for manufacturing a synchronous dynamic random access memory (SDRAM), comprising the steps of: (a) preparing a semiconductor substrate on which a gate insulating layer, a stacked gate having a polysilicon layer and a metal layer containing tungsten, and an insulating layer are formed; (b) forming a first oxide layer on the semiconductor substrate and sidewalls of the polysilicon layer, whereby a resulting structure is formed; (c) forming a first nitride layer on the resulting structure; (d) forming first nitride spacers on sidewalls of the metal layer, on the first oxide layer and on the gate insulating layer by applying a blanket etching process to the first nitride layer; (e) injecting dopants into the semiconductor substrate exposed at both sides of the first nitride layer spacers; (f) forming source/drain regions by activating the dopants through a thermal treatment in an O
2
atmosphere and simultaneously forming a second oxide layer on a surface of the substrate; and (g) forming second nitride layer spacers on sidewalls of the first nitride layer and on the second oxide layer.
The second oxide layer is formed to act as a buffer layer to the second nitride layer spacer, and it is preferably formed at a thickness of about 50 Å. Also, thermal treatment is carried out at a temperature of about 1000° C. for about 10 seconds.
REFERENCES:
patent: 5817562 (1998-10-01), Chang et al.
patent: 6165883 (2000-12-01), Hiura
patent: 6297137 (2001-10-01), Jung
patent: 6306743 (2001-10-01), Lee
patent: 6501114 (2002-12-01), Cho et al.
patent: 2000-156497 (2000-06-01), None
K. Kasai et al., W/WNx Poly-Si Gate Technology for Future High Speed Deep Submicron CMOS LSIs. IEDM 1994, pp. 497-500.*
M.T. Takagi et al., A Novel 0.15 micron CMOS Technology Using W/WNx/Polysilicon Gate Electrode and Ti Silicided Source/Drain Diffusions. IEDM 1996, pp. 455-458.*
B.H. Lee et al., In-Situ Barrier Formation for High Reliable W/Barrier/Poly-Si Gate Using Denudation of WNx on Polycrystalline Si. IEDM 1998. pp. 385-388.
Duy Mai Anh
Fahmy Wael
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
LandOfFree
Method for manufacturing synchronous DRAM device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing synchronous DRAM device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing synchronous DRAM device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3271919