Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-10-06
2002-03-05
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S108000, C438S121000, C228S180220, C029S840000, C029S843000
Reexamination Certificate
active
06352915
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly, to a bump grid array package which is an improvement of a ball grid array package, and a manufacturing method therefor.
2. Description of the Related Art
A general semiconductor package is manufactured by mounting a semiconductor chip on a pad or a substrate and molding the semiconductor chip using resin, with connection means electrically connected with an external circuit substrate being provided in the lower surface of the substrate.
Referring to
FIG. 1
showing a ball grid array package
10
which is a kind of the semiconductor package, a semiconductor chip
11
is bonded on a substrate
13
of the package
10
by a bonding agent
12
. Patterns
14
and
14
a
are formed on upper and lower surfaces of the substrate
13
, respectively. The patterns
14
and
14
a
are electrically connected with each other through a throughhole
16
formed to penetrate the substrate
13
. Also, the upper pattern
14
is wire-bonded to the semiconductor chip
11
by a bonding wire
15
, and a solder ball
17
is provided on the lower pattern
14
a.
Also, in order to protect the semiconductor chip
11
and the bonding wire
15
, the semiconductor chip
11
and the bonding wire
15
are molded using epoxy resin
18
. Here, a dam
19
is formed on a predetermined position of the substrate
13
so that the epoxy resin
18
may not spread too widely on the upper surface of the substrate
13
.
In fabricating the ball grid array package
10
, the solder ball
17
having a diameter of 0.75 mm or less is placed on the lower pattern
14
a
of the substrate
13
and then soldered at a high temperature to then be bonded to the lower pattern
14
a.
However, when the solder ball
17
is aligned on the lower pattern
14
a
for bonding the same thereon, the solder ball
17
may move, which causes misalignment of the solder ball
17
, generation of double balls due to neighboring balls sticking to each other, or missing balls.
SUMMARY OF THE INVENTION
To solve the above problems, it is desirable to provide a method for manufacturing a stable semiconductor package by employing bumps which are cylindrical or whose cross-sectional shapes are constant and a frame for supporting the bumps, and the semiconductor package manufactured thereby.
Accordingly, there is provided a method for manufacturing a semiconductor package comprising the steps of (a) forming a plurality of bumps on a metal frame and a bridge for connecting and supporting the bumps, (b) coating liquid solder on the bumps, (c) aligning the frame with respect to a semiconductor substrate where patterns are formed so that the bumps are positioned on the patterns, (d) soldering the bumps on the patterns, and (e) separating the bumps from the frame by breaking a connecting portion of the bumps and the bridge.
Here, the step (a) comprises the steps of coating a photosensitive material on the metal frame, exposing the metal frame using a mask where patterns corresponding to the bumps and the bridge are formed, developing the metal frame, and etching the metal frame to form the bumps and the bridge.
Also, the method may further comprise the step of forming a notch at an end of the bridge connected to the bumps.
Alternatively, it is preferred that the method further comprises the step of half-etching the end of the bridge to form fracture portions at the end of the bridge connected to the bumps.
According to another aspect of the present invention, a semiconductor package comprising a substrate, a semiconductor chip mounted on the upper surface of the substrate, a first pattern formed on the upper surface of the substrate to be electrically connected with the semiconductor chip, a second pattern formed on the lower surface of the substrate to be electrically connected with the first pattern through throughholes formed to penetrate the substrate, and bumps which are cylindrical or whose cross-sectional shapes are constant, bonded on the second pattern.
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patent: 5468999 (1995-11-01), Lin et al.
patent: 5765744 (1998-06-01), Tatumi et al.
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patent: 5969461 (2000-03-01), Anderson et al.
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Official Notice to Submit Response Letter dated Jun. 30, 2000, Korean Industrial Property Office.
Cho Young-rae
Lee Sang-kyun
Ryu Wook-yeol
Chambliss Alonzo
Chaudhuri Olik
Finnegan Henderson Farabow Garrett & Dunner LLP
Samsung Aerospace Industries Ltd.
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