Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2000-09-26
2004-07-06
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S201000, C438S591000, C438S593000, C438S680000, C438S681000, C438S769000, C438S770000, C438S786000, C257S314000, C257S390000
Reexamination Certificate
active
06759314
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-272322, filed Sept. 27, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a method for manufacturing semiconductor devices such as nonvolatile memories or MOS transistors using thermal nitride films as gate insulating films and more particularly to a method for manufacturing cell transistors of a NAND cell type EEPROM (Electrically Erasable and Programmable Read-Only Memory).
FIG. 1
is a pattern plan view showing the memory cell structure of a NAND cell type EEPROM (NAND cell type flash memory) and
FIG. 2
shows the equivalent circuit thereof. As shown in
FIGS. 1 and 2
, the current paths of a plurality of cell transistors CG
1
to CGn which are each formed of an n-channel MOSFET having a stacked gate structure including a floating gate and control gate are serially connected. The drain of the cell transistor CG
1
which is disposed on one end side of the current paths is connected to a bit line BLi (i=1, 2, . . .) via the current path of a selection n-channel MOS transistor Q
1
and the source of the cell transistor CGn which is disposed on the other end side of the current paths is connected to a source line (ground potential) SL via the current path of a selection n-channel MOS transistor Q
2
. The transistors GC
1
to CGn, Q
1
, Q
2
are formed in the same well region. The control gates of the cell transistors CG
1
to CGn are connected to word lines WL
1
to WLn which are each continuously formed in the row direction and the gates of the selection transistors Q
1
, Q
2
are respectively connected to selection lines SG
1
, SG
2
. Further, one-side ends of the respective word lines WL
1
to WLn are connected to connection pads for connection with a peripheral circuit via Al wirings. The connection pads are formed on an element isolation region.
Next, the outline of the manufacturing method of the cell transistors of the NAND cell type flash memory is explained with reference to
FIGS. 3A
to
3
G corresponding to a cross section taken along the
3
—
3
line of the pattern plan view of FIG.
1
.
First, a silicon oxide film
2
with a film thickness of 7 nm is formed on a silicon substrate
1
by use of the thermal oxidation method (FIG.
3
A).
Then, an oxynitride film
3
is formed by nitrifying the silicon oxide film
2
by use of NH
3
gas and then oxidizing the same (FIG.
3
B). The oxynitride film
3
acts as a first gate insulating film and is generally called a tunnel oxide film.
Next, a polysilicon film
4
with a film thickness of 200 nm having phosphor doped therein as impurity is formed on the oxynitride film
3
by use of the LPCVD method. The polysilicon film
4
is used as a first gate electrode. Generally, the polysilicon film
4
is called a floating gate. Then, a second gate insulating film
5
with a film thickness of 120 nm is formed on the floating gate
4
by use of the LPCVD method. After this, a polysilicon film
6
having phosphor doped therein as impurity is formed on the second insulating film
5
by use of the LPCVD method. The polysilicon film
6
is used as a second gate electrode and it is generally called a control gate. Then, an oxide film
7
is formed on the polysilicon film
6
by use of the LPCVD method (FIG.
3
C).
Further, a photoresist
8
is coated on the oxide film
7
and the oxide film
7
is processed into a desired pattern by use of the photoetching method (FIG.
3
D).
Next, the photoresist
8
is removed. The etching process is effected in a direction perpendicular to the main surface of the silicon substrate
1
by use of a dry etching method such as an RIE (Reactive Ion Etching) method with the patterned oxide film
7
used as a mask so as to sequentially form control gate
6
, second gate insulating films
5
and floating gates
4
(FIG.
3
E).
Then, in order to suppress the leak current in the end portion of the gate electrode, enhance the surface withstand voltage of high breakdown voltage MOS transistors of the peripheral circuit, that is, the withstand voltages of the gate insulating films
5
,
3
and eliminate the damage caused by ions doped into the gate oxide films
5
,
3
via the gate electrodes
6
,
4
in the RIE process, a silicon oxide film
9
is formed by use of a thermal oxidation method (FIG.
3
F). Generally, the above oxidation process is called a post oxidation process and the oxide film
9
formed at this time is called a post oxidation film.
After the post oxidation film
9
is formed, impurity is doped into the silicon substrate
1
by an ion-implantation process with the stacked gate structures STG of the control gates
6
and floating gates
4
used as a mask so as to form source and drain regions
10
and then the doped impurity is activated by annealing to form cell transistors (FIG.
3
G).
However, since the nitrogen concentration in the tunnel oxide film is high if the oxynitride film
3
is used as the tunnel oxide film as described above, it becomes difficult to form the post oxidation film
9
. Therefore, the damage caused in the tunnel oxide film
3
in the RIE process cannot be eliminated. Further, as shown by an enlarged portion in
FIG. 4
, the neighboring portion of the edge of the floating gate
4
is not oxidized and is formed in a sharpened shape.
In a flash memory, a state in which electrons exist in the floating gate
4
corresponds to a programmed state “0” and a state in which electrons do not exist in the floating gate
4
corresponds to an erase state “1”. Since electrons pass through the tunnel oxide film
3
in both directions to set up the programmed state and erase state, some electrons are trapped in the tunnel oxide film
3
to reduce a current amount if a damage D occurring in the RIE process is kept left in the tunnel oxide film
3
. Further, if a portion of the floating gate
4
is not oxidized at the time of post oxidation and is left behind with the corner portion sharpened, an electric field is concentrated on the above portion and degradation of the tunnel oxide film
3
will occur more rapidly.
As described above, in the conventional semiconductor device manufacturing method, the damage of the gate insulating film
3
caused at the etching time of the control gates
6
and floating gates
4
cannot be eliminated if the thermal nitride film is used as the first insulating film and there occurs a problem that electrons are trapped in the gate insulating film
3
to reduce a current amount and an electric field is concentrated on part of the gate insulating film
3
to accelerate the degradation thereof.
According to an aspect of the present invention, there is provided a semiconductor device manufacturing method comprising forming a gate insulating film in an oxynitride form on a main surface of a semiconductor substrate; forming gate electrodes on the gate insulating film; removing the gate insulating film except under the gate electrodes to expose the main surface of the semiconductor substrate; forming an insulating film on the exposed main surface of the semiconductor substrate by at least one of a vaporizer method using H
2
O as an oxidizer, an oxyhydrogen combustion method, and a wet oxidation method performed at temperatures not lower than 950° C.; and forming impurity diffused layers on both sides of the respective gate electrodes in the semiconductor substrate.
According to another aspect of the present invention, there is provided a semiconductor device manufacturing method comprising forming a gate insulating film in an oxynitride form on a main surface of a semiconductor substrate; forming gate electrodes on the gate insulating film; making a nitrogen concentration of the gate insulating film except under the gate electrodes lower than a nitrogen concentration of the gate insulating film which lies under the gate electrodes by oxidizing the gate electrodes and the gate insulating film by at least one of a vaporizer met
Fukazawa Yuji
Hazama Hiroaki
Kai Naoki
Moriyama Wakako
Nagai Keiki
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