Method for manufacturing semiconductor devices and plug

Details Method for manufacturing semiconductor devices and plug Method for manufacturing semiconductor devices and plug

2008-05-06

2008-05-06

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S267000, C438S270000, C438S597000, C257SE21495

Reexamination Certificate

active

11162081

ABSTRACT:
A method for manufacturing a semiconductor device is disclosed suitable for a substrate having a first conducting structure and a first dielectric layer, wherein the dielectric layer covers the first conductive structure. The method includes the steps of forming a second conductive structure over the substrate adjacent to the first conductive structure. Then, the size of the second conductive structure is reduced so that a top surface of the second conductive structure is relatively lower than that of the first conductive structure. Thereafter, a second dielectric layer is formed over the substrate to cover the first and the second conductive structure. A via is formed in the second dielectric layer to expose the top surface of the first conductive structure. Finally, a via plug is formed in the via.

REFERENCES:
patent: 6531350 (2003-03-01), Satoh et al.
patent: 6656825 (2003-12-01), Burbach
patent: 6943082 (2005-09-01), Shibata
patent: 6967143 (2005-11-01), Mathew et al.
patent: 6972260 (2005-12-01), Huang et al.
patent: 7098124 (2006-08-01), Huang et al.
patent: 2003/0186552 (2003-10-01), Amano et al.
patent: 2005/0037585 (2005-02-01), Park et al.

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