Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2003-01-22
2003-11-18
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S314000, C438S317000
Reexamination Certificate
active
06649458
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique which can be effectively used for the manufacturing of high frequency power amplifier which is mainly comprised of hetero junction bipolar transistors (HBT) which constitute ultrahigh-speed IC elements.
As a semiconductor device which exhibits high speed performance and low power consumption performance, a hetero junction bipolar transistor (hereinafter also referred to as HBT) has been known. This hetero junction bipolar transistor is used in a form that the transistor is incorporated into a high frequency power amplifier (RF power amplifying module) of a mobile communication terminal such as a portable cellular phone.
The HBT has a structure in which a sub-collector layer and a collector layer are sequentially laminated onto one surface (main surface) of a semiconductor substrate, a base layer is partially formed over the collector layer, and an emitter layer which is formed of a semiconductor having a wide band gap is partially formed over the base layer.
In a power amplifying device for transmission in a communication system, the HBT has now been used as a transistor. Such a semiconductor device is described in Japanese Laid-open Patent 210723/2001.
In Japanese Laid-open Patent 210723/2001, a technique for manufacturing a semiconductor device having a bias circuit which suppresses a change of an idle current attributed to a temperature change of a power transistor Tr
1
is disclosed. Such a semiconductor device is manufactured using a GaAs substrate as a base and, for compensating for a temperature shift of the idle current, a plurality of Schottky diodes are provided to a base inputting part. The bias circuit is constituted of two transistors (Tr
2
, Tr
3
) which are connected to the power transistor Tr
1
, two Schottky diodes (D
1
, D
2
) and three resisters (R
1
to R
3
).
That is, a base terminal of the power transistor Tr
1
is connected to a collector terminal of the transistor Tr
2
through a resistor R
3
in an emitter follower method, and a base terminal of the transistor Tr
2
is grounded through the transistor Tr
3
which short-circuits a base and a collector of the Schottky diodes D
1
, D
2
thus suppressing the change of the idle current C of the transistor Tr
1
which is generated when the temperature changes.
Further, with respect to this semiconductor device, base electrodes and the Schottky electrodes of the HBT are simultaneously formed at the time of manufacturing the semiconductor device.
On the other hand, in the manufacturing of the HBT, for preventing an excessive etching of the sub-collector layer, there has been known a technique which provides an InGaP layer between the sub-collector layer and the collector layer. This technique is described in IEEE Electron Device Lett., vol. 18, p355, 1997.
Further, in IEEE Electron Device Lett., vol. 18, p559, 1997, there is disclosed a technique which enhances the isolation performance by arranging an undoped InGaP layer having a resistance higher than a resistance of an undoped GaAs layer below a collector layer.
SUMMARY OF THE INVENTION
As a transistor which constitutes a high frequency power amplifier (RF power module) for a mobile communication unit, a hetero junction bipolar transistor (HBT) which constitutes a ultra high-speed IC element has been used. Further, to compensate for a temperature shifting of an idle current in the transistor, a bias circuit which provides a plurality of Schottky diodes to a base inputting part is incorporated. Resistance elements are also incorporated in this bias circuit.
The reduction of manufacturing cost has been requested with respect to the HBT in the same manner as other transistors and modules. With respect to the power transistor into which the bias circuit is incorporated, as described in the above-mentioned literature, there has been proposed the method which simultaneously forms the Schottky electrodes and the base electrodes using a same material.
To explain manufacturing steps thereof, as shown in FIG.
23
(
a
), a semiconductor layer (n
+
type GaAs layer) below an emitter electrode
56
is etched using the emitter electrode
56
as a mask until the etching reaches a surface of a semiconductor layer (n type InGaP layer) which constitutes a wide gap emitter layer
54
below the semiconductor layer (n
+
type GaAs layer) thus forming a mesa-shaped emitter layer
55
.
Thereafter, an etching mask not shown in the drawing is formed and, as shown in FIG.
23
(
a
), using this etching mask as a mask, a semiconductor layer which constitutes the wide gap emitter layer
54
which is exposed in a periphery of the emitter layer
55
, a semiconductor layer (p-type GaAs layer) which constitutes a base layer
53
below the semiconductor layer, and a semiconductor layer (n
+
type GaAs layer)
52
a
which constitutes a collector layer below the base layer
53
are sequentially etched, wherein the semiconductor layer
52
a
is etched to an intermediate depth thereof, thus forming the base layer having a mesa shape (mesa-shaped base layer)
53
.
Subsequently, a base electrode
57
and a Schottky electrode
58
are simultaneously formed, wherein the base electrode
57
is formed over the wide gap emitter layer
54
in the periphery of the emitter layer
55
and the Schottky electrode
58
is formed over the semiconductor layer (n
+
type GaAs layer)
52
a
which constitutes a collector layer in a Schottky diode forming region which is disposed away from a region where the HBT is formed. The base electrode
57
is subjected to an alloying treatment (heating treatment).
As a result, the wide gap emitter layer
54
below the base electrode
57
is alloyed so that a base electrode
57
and the base layer
53
are electrically connected to each other.
Further, in the manufacturing of the HBT, as shown in FIG.
23
(
a
), a substrate (wafer) which is eventually produced by sequentially forming respective semiconductor layers consisting of a sub collector layer
51
, the collector layer
52
, the mesa-shaped base layer
53
, the wide gap emitter layer
54
and the emitter
55
over one surface (main surface) of a semi-insulation GaAs substrate
50
is used.
However, in the method which forms the base electrode over the semiconductor layer which constitutes the wide gap emitter layer
54
, it is necessary to form holes for forming the base electrode in the etching mask. Accordingly, in view of the mask alignment tolerance for forming this hole, it is necessary to ensure the mask alignment tolerance length between an outer periphery of the base electrode
57
and an outer periphery of a mesa-shaped base layer
53
in FIG.
23
(
b
). As a result, a junction area between the base layer
53
and the collector layer
52
is increased. The increase of the area between the base and the collector deteriorates the high frequency characteristics (for example, maximum oscillation frequency f max).
Then, as shown in
FIG. 24
, when the mask alignment tolerance length is shortened, the outer periphery of the base electrode
57
extends beyond the periphery of the mesa-shaped base layer
53
and is brought into contact with the collector layer
52
(contact portion
70
) thus giving rise to a short-circuit defect. This leads to the lowering of a yield factor and brings about a drawback that a manufacturing cost is pushed up.
To prevent the outer periphery of the base electrode
57
from extending beyond the mesa-shaped base layer
53
and coming into contact with the semiconductor layer (n
+
type GaAs layer)
52
a
which constitutes the collector layer, it is necessary to ensure a minimum mask alignment tolerance length “a”.
FIG. 25
is a schematic view for showing the size relationship among respective portions in the manufacturing of the HBT while ensuring the mask alignment tolerance length “a”.
A base-collector junction length L
2
is a length which is obtained by adding 2×mask alignment tolerance length “a” to a dist
Imamura Yoshinori
Inagawa Hiroshi
Kitahara Toshiaki
Kurokawa Atsushi
Chaudhari Chandra
Hitachi , Ltd.
Miles & Stockbridge P.C.
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