Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
2006-09-25
2009-08-04
Malsawma, Lex (Department: 2892)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
C257S207000, C257S691000, C257SE23024, C361S777000
Reexamination Certificate
active
07569428
ABSTRACT:
Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.
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Japanese Office Action, with partial English translation, issued in Japanese Patent Application No. 2005-283020, mailed Apr. 7, 2009.
Fujisawa Hiroki
Isa Satoshi
Itaya Satoshi
Katagiri Mitsuaki
Osanai Fumiyuki
Elpida Memory Inc.
Malsawma Lex
McDermott Will & Emery LLP
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