Method for manufacturing semiconductor device having element...

Details Method for manufacturing semiconductor device having element... Method for manufacturing semiconductor device having element...

2001-11-16

2003-02-25

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S406000, C438S424000, C438S459000

Reexamination Certificate

active

06524890

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for manufacturing a semiconductor device adopting an element isolation structure.
2. Description of the Related Art
An SOI (Silicon On Insulator) structure is conventionally known as an element isolation structure.
FIGS. 4A
to
4
F show a process for manufacturing a semiconductor device in which element isolation is achieved by an SOI structure, and the method for manufacturing this semiconductor device is explained below.
First, as shown in
FIG. 4A
, oxide films
13
a,
13
b
are respectively formed, by surface oxidation, on a support wafer
11
and a wafer
12
for element formation (element formation wafer) each of which is composed of a silicon wafer. After that, the surfaces of the oxide films
13
a,
13
b
are bonded together, and accordingly, an SOI substrate shown in
FIG. 4B
is formed, in which the support wafer
11
and the element formation wafer
12
are bonded together with an oxide film
13
interposed between them.
Successively, as shown in
FIG. 4C
, the element formation wafer
12
is mechanically polished until the thickness of the element formation wafer
12
falls in a range of several &mgr; m to about 20 &mgr;m, and mirror finishing is performed. Then, as shown in
FIG. 4D
, trenches
14
are formed such that the trenches
14
extend from the surface of the element formation wafer
12
to the oxide film
13
. Element isolation is performed by filling the trenches
14
with an oxide film or poly silicon.
After that, elements (not shown) are formed in respective regions that are isolated from one another, and as shown in
FIG. 4E
, the SOI substrate is divided into chips. Then, as shown in
FIG. 4F
, for example, a chip is die-mounted on a substrate
17
such as a metallic plate through conductive paste
16
. Thus, a semiconductor device that has isolated elements due to the SOI structure is finished. In this constitution, however, because the bonding wafer having the support wafer
11
is necessitated, the cost is high because of the number of processes required.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above problems. An object of the present invention is to simplify a method for manufacturing a semiconductor device having an element isolation structure.
According to the present invention, briefly, after a trench is formed in a wafer from a principal surface of the wafer, the trench is filled with an insulating film. Then, the thickness of the wafer is thinned from a back surface of the wafer so that the insulating film is exposed on the back surface. Accordingly, element isolation of the wafer can be achieved by the insulating film penetrating the wafer from the principal surface to the back surface. It is not necessary to use a bonding wafer. As a result, the method for manufacturing the semiconductor device can be simplified.


REFERENCES:
patent: 3457123 (1969-07-01), Pul
patent: 4501060 (1985-02-01), Frye et al.
patent: 4784970 (1988-11-01), Solomon
patent: 4839309 (1989-06-01), Easter et al.
patent: 5091330 (1992-02-01), Cambou et al.
patent: 5204282 (1993-04-01), Tsuruta et al.
patent: 5449946 (1995-09-01), Sakakibara et al.
patent: 5459104 (1995-10-01), Sakai
patent: 5502289 (1996-03-01), Takiar
patent: 5773352 (1998-06-01), Hamajima
patent: 6177359 (2001-01-01), Chen et al.
patent: 6225191 (2001-05-01), Ahlquist et al.
patent: A-59-186345 (1984-10-01), None
patent: A-63-302552 (1988-12-01), None
patent: A-9-8126 (1997-01-01), None
patent: A-11-307488 (1999-11-01), None
patent: A-2000-195825 (2000-07-01), None
patent: A-2001-144173 (2001-05-01), None
Stanley Wolf,Silicon Processing for the VLSI ERA, vol. 2: Process Integration, Lattice Press, pp. 69-71, 1990.
Yamazaki and Aoyama, “Analysis in Function of Polishing Pad Grooves in CMP Apparatus,” Jul. 19, 1999.

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