Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-10-29
2002-11-05
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S692000, C438S696000, C438S699000, C438S628000
Reexamination Certificate
active
06475901
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and in particular, the present invention relates to the formation of a multi-layer interconnection of a semiconductor device.
2. Description of the Related Art
With the miniaturization of semiconductor devices, it has become necessary to form multi-layer interconnection structures. The width of corresponding interconnects and the spacing between such interconnects of a lower layer interconnect pattern are especially reduced with the miniaturization of semiconductor devices. To provide an interlayer insulating film for a semiconductor device which includes multi-layer interconnect patterns, an insulating film made of silicon oxide which has a reduced dielectric constant is primarily used for the purpose of reducing parasitic capacitance between an upper (or overlying) interconnect layer and a lower (or underlying) interconnect layer, as well as between interconnects in the same layer. A High Density Plasma (HDP) CVD method is used to fill a gap between interconnects with the interlayer insulating film.
However, fluorine, which is included in the interlayer insulating film (silicon oxide layer) to reduce the dielectric constant, corrodes the interconnects. Hydrogen fluoride is formed by hydrolysis of fluorine with the moisture content of air, and interconnects, which contact to the silicon oxide layer, are corroded by the hydrogen fluoride. A fluoride gas is also formed in a process after the formation of the silicon oxide layer, and this also corrodes the interconnects. Therefore, the interconnects must be prevented from touching the silicon oxide layer which includes fluorine.
For gap filling, HDP CVD processing is a simultaneous deposition/etching process in which loosely deposited silicon oxide films are sputtered off by reactive ions and radicals during deposition. Fluorine in the etched silicon oxide layer is diffused into the silicon oxide layer between interconnects. Therefore, the quality of the silicon oxide layer filled in gaps of the interconnects is different from the silicon oxide layer of other portions. That is, the quality of silicon oxide layer filled in gaps is inferior to the silicon oxide layer of other portions with respect to moisture resistance.
Because of the above described problems, impurity (fluorine) concentration must be low, and the HDP CVD method costs about three times more than the methods using a parallel plate CVD apparatus.
Also, the case where an overlay shift occurs during photo lithography, a short-circuit is formed between the contact and interconnect.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a semiconductor device generally includes a semiconductor substrate, a plurality of first interconnects formed over the semiconductor substrate, a first insulating layer covering the plurality of first interconnects, a second insulating layer formed between the plurality of first interconnects, the second insulating layer having substantially the same height as the plurality of first interconnects, and an intermediate insulating layer formed over the second insulating layer.
REFERENCES:
patent: 5817571 (1998-10-01), Yu et al.
patent: 6048800 (2000-04-01), Nagashima et al.
patent: 6218284 (2001-04-01), Liu et al.
patent: 61-181192 (1994-06-01), None
patent: 9-266207 (1997-10-01), None
Nakamura Makiko
Nishimura Hidetomo
Oki Electric Industry Co. Ltd.
Tsai Jey
Volentine Francos P.L.L.C.
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