Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-04-06
2001-07-17
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S634000, C438S622000, C438S624000, C438S638000, C438S627000, C438S643000, C257S750000, C257S751000, C257S758000
Reexamination Certificate
active
06261949
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device for forming a contact hole and a wiring embedding groove in an interlayer insulation film and then forming a multilayer metal wiring.
2. Description of the Related Art
There is a limit to increasing a two-dimensional wiring region in a semiconductor device. To overcome this limit, a multilayer wiring structure which is a three-dimensional wiring structure has been provided. The multilayer wiring structure requires reducing inter-wiring capacity to thereby decrease an impedance.
A technique for embedding a wiring into an interlayer insulation film is known as one of methods for forming a multilayer wiring. Among those embedded wiring formation techniques, particularly, a so-called dual damascene process (or an interlayer wiring method) for forming a groove for embedding a contact hole and a wiring into an interlayer insulation film, then embedding a conductive material into the contact hole to form a contact and, at the same time, embedding a conductive material into the groove to form a metal wiring is disclosed by, for example, Japanese Patent Application Laid-Open No. 9-306988.
The interlayer wiring formation method includes, first, as shown in
FIG. 1A
, forming an interlayer insulation film (silicon oxide film)
602
on a conductive material
601
, coating a photo resist
604
after growing an interlayer nitride film
603
serving as a stopper and forming a contact hole pattern on the interlayer nitride film
603
by normal photolithography and dry etching. In this case, the contact hole pattern is only formed on the interlayer nitride film
603
.
Next, as shown in
FIG. 1B
, after removing the photo resist
604
, an interlayer insulation film (silicon oxide film)
606
is grown.
As shown in
FIG. 1C
, after the photo resist
607
is coated on the interlayer insulation film
606
, a pattern for a wiring groove is formed on the photo resist
607
by photolithography. Using this photo resist
607
as a mask, the interlayer insulation films
606
and
602
are etched under the condition that the etch selectivity of the oxide film to the nitride film is high. By so doing, the interlayer insulation film
606
is etched and a wiring groove
608
is formed. Also, the interlayer insulation film
602
is preferentially etched over the interlayer nitride film
603
, so that the interlayer insulation film
602
is etched with the interlayer nitride film
603
used as an etch mask and a contact hole
605
is formed.
Next, as shown in FIG. ID, the photo resist
607
is removed and metal films
609
and
610
, which become wirings, are deposited into the contact hole
605
and the wiring groove
608
as well as on the interlayer insulation film
606
. Finally, the metal films
609
and
610
are removed by CMP (Chemical Mechanical Etching) or dry etching. The metal film
610
is left within the contact hole
605
and the wiring groove
608
so that the metal film
610
is flush with the interlayer insulation film
606
, thereby completing an embedded wiring consisting of the metal films
609
and
610
.
According to the embedded wiring formation method using the above-stated dual damascene process, however, since the interlayer insulation film
602
is etched with the interlayer nitride film
603
used as a mask, it is necessary not to complete etching the interlayer nitride film
603
before the contact hole
605
penetrating the interlayer insulation film
602
is formed. For that reason, the interlayer nitride film
603
has to be formed thick. If the interlayer nitride film
603
is made thicker, however, the interlayer nitride film
603
covered with the interlayer insulation film
606
remains thick to disadvantageously increase inter-wiring capacity. In other words, a plasma oxide film is normally used as an interlayer insulation film. The dielectric constant of the nitride film is higher than that of the plasma oxide film. The thickness of the interlayer insulation film needs to be constant in light of the necessity of leak characteristics and the like. As a result, if the thickness of the nitride film which replace the oxide film is large, i.e., if the ratio of the nitride film to the insulating film is high, inter-wiring capacity increases due to the thick nitride film.
If the inter-wiring capacity increases, the problem of signal delay occurs, thereby disadvantageously hampering the recent demand to provide a higher-speed semiconductor device.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming an embedded wiring without increasing the capacity of an interlayer wiring.
A method for manufacturing a semiconductor device according to the present invention is characterized by comprising the steps of:
forming a first interlayer insulation film on a conductive material;
forming a contact hole in the first interlayer insulation film;
forming a second interlayer insulation film on the first interlayer insulation film while making the contact hole remain cavity;
forming a resist film for a wiring groove pattern on the second interlayer insulation film;
forming a wiring groove in the second interlayer insulation film by etching the second interlayer insulation film with the resist film used as a mask, and opening the contact hole confined by the second interlayer insulation film; and
forming a wiring and a contact by embedding metal material into the wiring groove and the contact hole.
Another method for manufacturing a semiconductor device according to the present invention is characterized by comprising the steps of:
forming a first interlayer insulation film on a conductive material;
forming a first resist film on the first interlayer insulation film;
forming a contact hole pattern on the first resist film;
forming a contact hole in the first interlayer insulation film by etching the first interlayer insulation film with the first resist film used as a mask;
forming a second interlayer insulation film on the first interlayer insulation film while making the contact hole remain a cavity;
forming a second resist film on the second interlayer insulation film;
forming a wiring groove pattern on the second resist film;
forming a wiring groove in the second interlayer insulation film by etching the second interlayer insulation film with the second resist used as a mask, and opening the contact hole confined by the second interlayer insulation film; and
forming a wiring and a contact by embedding metal material into the wiring groove and the contact hole.
According to the present invention, it suffices for the nitride film which has been conventionally used as a mask when etching the contact hole formed between the first interlayer insulation film and the second interlayer insulation film to only function as an etching stopper layer. Thus, the etching stopper film itself can be extremely made thinner than the nitride film used as the conventional mask. In addition, by selecting etching conditions appropriately, it is possible to dispense with the etching stopper film itself. Thus, according to the present invention, interlayer capacity can be reduced. Furthermore, according to the present invention, it is possible to form a contact hole using not the nitride film but the resist film as a mask, so that a contact hole of a desired diameter can be formed with good repeatability.
Hence, according to the present invention, it is possible to reduce inter-wiring capacity and prevent signal delay in the dual damascene process, so that the present invention is quite useful for making a semiconductor device smaller in size and higher in speed.
REFERENCES:
patent: 5672543 (1997-09-01), Chang et al.
patent: 5807761 (1998-09-01), Coronel et al.
patent: 5893752 (1999-04-01), Zhang et al.
patent: 5920790 (1999-07-01), Wetzel et al.
patent: 0 720 223 (1996-07-01), None
patent: 9-153545 (1997-06-01), None
patent: 9-306966 (1997-11-01), None
patent: 10-261707 (1998-
Bowers Charles
Lee Hsien-Ming
NEC Corporation
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