Method for manufacturing semiconductor device

Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – On insulating substrate or layer

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S513000, C438S527000, C438S717000

Reexamination Certificate

active

08030187

ABSTRACT:
A substrate is exposed to a plasma generated from a gas containing an impurity, thereby doping a surface portion of the substrate with the impurity and thus forming an impurity region. A predetermined plasma doping time is used, which is included within a time range over which a deposition rate on the substrate by the plasma is greater than 0 nm/min and less than or equal to 5 nm/min.

REFERENCES:
patent: 4496450 (1985-01-01), Hitotsuyanagi et al.
patent: 4696883 (1987-09-01), Saitoh et al.
patent: 6403410 (2002-06-01), Ohira et al.
patent: 7192854 (2007-03-01), Sasaki et al.
patent: 7348264 (2008-03-01), Sasaki et al.
patent: 7759254 (2010-07-01), Sasaki et al.
patent: 2003/0153101 (2003-08-01), Takase et al.
patent: 2006/0099830 (2006-05-01), Walther et al.
patent: 2007/0111548 (2007-05-01), Sasaki et al.
patent: 2007/0176124 (2007-08-01), Sasaki et al.
patent: 2008/0067439 (2008-03-01), Sasaki et al.
patent: 2008/0233723 (2008-09-01), Okumura et al.
patent: 2008/0258082 (2008-10-01), Okumura et al.
patent: 2009/0042321 (2009-02-01), Sasaki et al.
patent: 2009/0227096 (2009-09-01), Godet et al.
patent: 2010/0009469 (2010-01-01), Kai et al.
patent: 64-061020 (1989-03-01), None
patent: WO 02/084724 (2002-10-01), None
patent: WO 2005/034221 (2005-04-01), None
patent: WO 2006/064772 (2006-06-01), None
patent: WO 2006/121131 (2006-11-01), None
Y, Sasaki et al., “B2H6Plasma Doping with ‘In-situ He Pre-amorphization,’” 2004 Symposium on VLSI Technology, p. 180-181.
Y. Sasaki et al., “Production-Worth USJ Formation by Self-Regulatory Plasma Doping Method,” CP866 Ion Implantation Technology, 2006 American Institute of Physics, pp. 524-527.
Y. Sasaki et al., “New method of Plasma doping with in-situ Helium pre-amorphization,” Nuclear instruments and Methods in Physics Research B 237 (2005) pp. 41-45.
D. Lenoble, “Advanced junction fabrication challenges at the 45nm node,” Semiconductor Fabtech-30th Edition, pp. 114-130.
Shu Qin et al., “Device Performance Evaluation of PMOS Devices Fabricated by B2H6PIII/PLAD Process of Poly-Si Gate Doping,” International Workshop in Junction Technology, pp. 68, 2006.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for manufacturing semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing semiconductor device will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4255717

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.