Method for manufacturing semiconductor device

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S603000, C438S681000, C257SE21170, C257SE21006, C257SE21126, C257SE21127, C257SE21129, C257SE21134, C257SE21320

Reexamination Certificate

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07825020

ABSTRACT:
Disclosed herein is a method of manufacturing a semiconductor device that includes forming a metal catalytic pattern on a semiconductor substrate; etching the semiconductor substrate using the metal catalytic pattern as an etching mask to form a recess; forming an insulating layer over a structure including the recess, the metal catalytic pattern, and the semiconductor substrate; patterning the insulating layer to cross over the metal catalytic pattern and to expose a predetermined portion of the metal catalytic pattern; and growing a nano wire using the exposed predetermined portion of the metal catalytic pattern.

REFERENCES:
patent: 6322713 (2001-11-01), Choi et al.
patent: 6340822 (2002-01-01), Brown et al.
patent: 7354850 (2008-04-01), Seifert et al.
patent: 2004/0005258 (2004-01-01), Fonash et al.
patent: 2008/0142926 (2008-06-01), Seifert et al.
patent: 10-2005-0062778 (2005-06-01), None
patent: 10-2006-0096886 (2006-09-01), None
patent: 10-2007-0038786 (2007-04-01), None
patent: 10-2008-0007682 (2008-01-01), None

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