Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2008-02-04
2009-11-24
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S412000, C438S421000, C438S422000, C257SE21533
Reexamination Certificate
active
07622359
ABSTRACT:
A method for manufacturing a semiconductor device, includes: (a) forming a SiGe layer on a Si substrate; (b) forming a Si layer on the SiGe layer; (c) forming a dummy pattern made of SiGe in a dummy region of the Si substrate; and (d) wet-etching and removing the SiGe layer formed under the Si layer. In the step (d), an etchant is kept to contact the dummy pattern from before a complete remove of the SiGe layer to an end of the etching.
REFERENCES:
patent: 2006/0223270 (2006-10-01), Hara
patent: 2007/0080402 (2007-04-01), Kato
patent: 2007/0176236 (2007-08-01), Oka et al.
patent: 2007/0296000 (2007-12-01), Hara
patent: 2009/0170293 (2009-07-01), Matsuzawa
patent: 2005-354024 (2005-12-01), None
T. Sakai et al. “Separation by Bonding Si Islands (SBSI) for LSI Applications”, Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004).
Kanemoto Kei
Kato Juri
Fourson George
Harness & Dickey & Pierce P.L.C.
Seiko Epson Corporation
LandOfFree
Method for manufacturing semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4143778