Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2006-07-18
2009-12-08
Smith, Matthew (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S216000, C438S287000, C438S537000, C257SE21625, C257SE21639
Reexamination Certificate
active
07629243
ABSTRACT:
A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex(0≦x<0.25), subjecting the first layer to a first heat treatment wherein the first layer is heated for 1 msec or less at a temperature higher than 1100° C., forming a second layer on the first layer, the second layer containing a second p-type impurity and formed of amorphous silicon or polycrystalline silicon, the second p-type impurity having a smaller covalent bond radius than that of the first p-type impurity, and subjecting the second layer to a second heat treatment to heat the second layer at a temperature ranging from 800° C. to 1100° C.
REFERENCES:
patent: 5403458 (1995-04-01), Hartig et al.
patent: 6667525 (2003-12-01), Rhee et al.
patent: 2004/0129988 (2004-07-01), Rotondaro et al.
patent: 2004/0235280 (2004-11-01), Keys et al.
patent: 2005/0181585 (2005-08-01), Yamauchi et al.
patent: 2006/0102968 (2006-05-01), Bojarczuk et al.
patent: 2002-299282 (2002-10-01), None
patent: 2004-119513 (2004-04-01), None
patent: 2004-214673 (2004-07-01), None
patent: 2005-136382 (2005-05-01), None
patent: WO 2004/086508 (2004-10-01), None
Seiple et al., “Evolution of atomic-scale roughening on Si(001)−(2×1) surfaces resulting from high temperature oxidation,” J. Vac. Sc. Technol. A (May/Jun. 1995), 13:772-776.
White, C. W. et al., “Supersaturated Substitutional Alloys Formed by Ion Implantation and Pulsed Laser Annealing of Group-III and Group-V Dopants in Silicon,” J. Appl. Phys., vol. 51, No. 1, pp. 738-749, (Jan. 1980).
Notice of Reasons for Rejection mailed Jul. 22, 2008, from the Japanese Patent Office in counterpart Japanese Application No. 2005-208915.
Notice of Reasons for Rejection mailed Mar. 10, 2009, from the Japanese Patent Office in counterpart Japanese Application No. 2005-208915, and English language translation thereof.
Final Notice of Rejection mailed Sep. 8, 2009, in corresponding Japanese patent application No. 2005-208915, and English-language translation of same.
Aoki Nobutoshi
Ino Tsunehiro
Kaneko Akio
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Jefferson Quovaunda
Kabushiki Kaisha Toshiba
Smith Matthew
LandOfFree
Method for manufacturing semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4136039