Method for manufacturing printed wiring board

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S624000, C438S637000, C438S508000

Reexamination Certificate

active

07968449

ABSTRACT:
A method for manufacturing a printed wiring board having one or more layers of a conductive pattern and an insulating pattern, including forming an insulating pattern on an insulating substrate; semi-hardening at least one of the insulating substrate and the insulating pattern; forming a conductive pattern on the insulating substrate and/or the insulating pattern, thereby providing a stack structure; performing a thermal treatment on the stack structure to fully harden the semi-hardened insulating substrate and/or insulating pattern; and firing the conductive pattern. In the method, the conductive pattern and the insulating pattern are simultaneously formed on the same layer using an inkjet process.

REFERENCES:
patent: 5698470 (1997-12-01), Yamaguchi
patent: 6010956 (2000-01-01), Takiguchi
patent: 2003/0213614 (2003-11-01), Furusawa et al.
patent: 11-163499 (1999-06-01), None
patent: 2004-241514 (2004-08-01), None
patent: 2005-210079 (2005-08-01), None
U.S. Appl. No. 11/634,970, filed Dec. 7, 2006, Hye Jin Cho et al., Samsung Electronics Co., Ltd.
Japanese Office Action dated Oct. 13, 2009, issued in corresponding Japanese Patent Application No. 2006-331065.
Office Action mailed Mar. 18, 2009 in file history of U.S. Appl. No. 11/634,970.
Office Action mailed Sep. 8, 2009 in file history of U.S. Appl. No. 11/634,970.
Notice of Allowance mailed Dec. 31, 2009 in file history of U.S. Appl. No. 11/634,970.

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