Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-03-09
2002-05-14
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S614000
Reexamination Certificate
active
06387793
ABSTRACT:
I. BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of solder bump structures compatible with group III-V semiconductor materials. More particularly, the present invention pertains to the use of a novel electroplating method of fabrication of the solder bumps which method does not damage air bridges, micro-electromechanical structures, or optical surfaces that can be otherwise damaged if conventional methods for fabricating solder bumps are used.
2. Description of the Related Art
Prior or related art teaches methods of fabrication of a number of solder bump structures. The prior art methods include a method of vacuum evaporation and a method of electroplating.
The structure shown in FIG.
1
(
a
) contains a solder bump formed by deposition in a vacuum evaporator. See W. R. Imler, et al., IEEE Transactions on Components, Hybrids, and Manufacturing Technology, v. 15, p. 977, 1992. The solder bump resides above a multilayer pad that consists of titanium, tungsten nitride, nickel alloy, and gold. This structure also contains an oxidized silicon passivation film which serves as a non-wettable dam to constrain the solder wet back. The solder bumps are deposited through metal shadow masks clamped over the surface of the substrate wafer. A solder pad diameter of 75 micrometers at a pitch of 156 micrometers has been achieved with this technique. A disadvantage of the shadow-masked evaporation method is that solder bumps having smaller diameter and finer pitch are difficult to achieve yet such smaller diameter and finer pitch bumps are often needed.
The structure shown in FIG.
1
(
b
) contains a solder bump formed by electroplating. See T. Kawanobe, K. Miyamoto, and Y. Inaba, IEEE publication CH1671-7/0000, p. 149, 1981. The solder bump resides on multilayer underbump metallization (hereinafter, UBM) that consists of titanium and copper films and an electroplated nickel pad. A 2 micrometer thick copper film serves as a plating membrane for the electroplating of the lead/tin solder. The titanium film is designed to serve as an adhesion layer between the copper film and the underlying aluminum metallization, passivation film or silicon substrate. After the electroplating, the copper and titanium films are wet etched away, leaving only a small pad of UBM material underneath the solder. Electroplated solder bumps can have quite fine pitch, e.g. 50 micrometer diameter pads with 100 micrometer pitch is typical.
However, when the solder bump is formed by electroplating, the plating membrane must be removed subsequently in order to avoid short circuiting the various solder bump joints that exist on a substrate. It is difficult to find suitable underbump metallization and plating membrane materials that can be etched away without also attacking the solder or the underlying circuitry. Copper is typically used as the plating membrane because its etchant does not attack the lead/tin solder. Copper, however, is not compatible with group III-V semiconductor materials. In addition to avoiding an attack on the solder bump itself, some provision is needed to protect the circuit elements from attack by the plating bath and by the etchants used to remove the membrane. In the structure of FIG.
1
(
b
), a permanent passivation film, formed underneath the UBM and typically consisting of silicon dioxide or polyimide, protects the circuit elements. That passivation film also serves as a non-wettable surface or solder dam which causes the plated solder to wet back onto the pad.
The known electroplating method described above has some serious disadvantages and is not usable with group III-V semiconductor materials. In addition to the impossibility to use copper due to its incompatibility with group III-V semiconductor materials, for some MMICs, microelectromechanical elements or optoelectronic devices, it may not be possible to protect key features such as air bridges, cantilever beams or optical coatings and surfaces with a permanent passivation film. A removable protective film is needed. Another need is to have a solder dam that covers only the vicinity of the solder bump. Also needed is a plating membrane that both is compatible with group III-V materials and that can be etched away without attacking the plated solder.
For the foregoing reasons, there is a need for a method of fabrication of a solder bump having a small diameter and a very fine pitch, where a removable protective film is utilized. The plating membrane is needed that is compatible with group III-V semiconductor materials and that can be etched away without attacking the plated solder. The present invention offers such a solder bump and the method of manufacturing thereof.
II. SUMMARY OF THE INVENTION
The present invention is directed to a method of fabrication of a solder bump allowing to obtain very fine size bumps while a solder dam preferably only covers space in a vicinity of the bump. The method uses a plating membrane compatible with group III-V semiconductor materials and also with group IV semiconductor materials. After the completion of the fabrication process, the membrane is safely removed and the solder is unaffected by the agent used to remove the membrane. This invention is also directed to the solder bump structure obtained as a result of utilization of this method.
The solder bump structure and fabrication method of this invention avoid the need for depositing a permanent layer over the circuits to protect them from the solder-bump processing. Such a permanent layer can alter the performance of the circuits and devices. In accordance with the invention it is now possible to fabricate electroplated solder bumps while simultaneously protecting the circuit elements from such altered performance. For example, circuits for wireless communications may contain inductors, transmission lines or transistors that have air bridges which would be adversely affected by a permanent layer such as one found in the prior art. Also, future high-speed, high-density interconnects between processors may be based on chips of solder-bumped optoelectronic devices which also should not be covered by such a layer.
This invention uses a metal film, preferably of titanium, deposited above the protective film, to serve both as a plating membrane and a solder dam and uses a photodefinable polyimide, a spin-on glass, a spin-on conductive polymer,or, preferably, a photoresist as a removable protective film. The photoresist can be removed, after the solder plating and membrane etching, by solvents that do not attack the solder. The titanium film can be wet etched without attacking either the solder or the underlying circuit elements. The thickness of the titanium film is generally between 0.05 and 0.2 micrometers and is readily deposited onto the photoresist protective film. This thickness of titanium is significantly thinner than that of other films used previously as plating membranes. The suitability of a thin titanium film as a membrane for electroplating of solder is unexpected. The method does not require the use of copper.
III. BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:
FIG.
1
(
a
) is a schematic diagram showing prior art of fabricating solder bumps by shadow mask evaporation method.
FIG.
1
(
b
) is a schematic diagram showing prior art of fabricating solder bumps by electroplating method.
FIG. 2
is a schematic diagram showing a preferred embodiment of the solder bump structure of this invention.
FIG.
2
(
a
) is a plan view of the structure shown on
FIG. 2
showing the same structure from above.
FIG.
2
(
b
) is a schematic diagram showing the structure of the preferred embodiment of the underbump metallization layer.
FIG. 3
is a schematic diagram showing a detailed illustration of interface between the solder, the pad, and the solder dam in the solder bump structure of this invention, including the use of a titanium sealant feature.
FIG.
Lawyer Phillip H.
Yap Daniel
Bowers Charles
HRL Laboratories LLC
Kebede Brook
LandOfFree
Method for manufacturing precision electroplated solder bumps does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing precision electroplated solder bumps, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing precision electroplated solder bumps will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2888558