Method for manufacturing planar field effect transistors and pla

Details Method for manufacturing planar field effect transistors and pla Method for manufacturing planar field effect transistors and pla

1996-08-21

1998-12-29

Dutton, Brian

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

438571, 438577, H01L 2166, H01L 2128, H01L 2144, G01R 3126

Patent

active

058540865

ABSTRACT:
An apparatus and method of processing a planar HEMT or FET semiconductor device is disclosed. An ohmic metalization is patterned on a semiconductor surface then lifted-off. A plurality of process control monitors are isolated, preferably using a wet etch process. The process control monitors preferably include transmission line patterns (TLMs) and etch field effect transistors The TLMs measure the contact resistance during the ohmic alloy process, and the etch field effect transistors monitor the drain current during the gate-recess step. The ohmic metalizations are then alloyed, and a gate is written using an electron beam. The semiconductor device is isolated, followed by application of an overlay which connects all resulting planar device connecting pads.

REFERENCES:
patent: 5038187 (1991-08-01), Zhou
patent: 5053348 (1991-10-01), Mishra et al.
patent: 5646069 (1997-07-01), Jelloian et al.
Bahl, Sandeep R., et al. "Elimination of Mesa-Sidewall Gate Leakage in InA1As/InGaAs Heterostructures by Selective Sidewall Recessing," Apr., 1992 IEEE Electron Device Leters, vol. 13, No. 4, pp. 195-197.
Bahl, Sandeep R. et al.., "Mesa-Sidewall Gate Leakwage in InA1As/InGaAs Heterostructure Field-Effect Transistors" Sep., 1992, IEEE Transactions on Electron Devices, vol. 39, No. 9, pp. 2037-2043.

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