Method for manufacturing offset polysilicon thin-film transistor

Details Method for manufacturing offset polysilicon thin-film transistor Method for manufacturing offset polysilicon thin-film transistor

1994-12-27

1996-08-06

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437192, 437200, 148DIG147, H01L 21336

Patent

active

055433405

ABSTRACT:
In a method for fabricating an offset polysilicon thin-film transistor through the formation of silicide, the width of offset regions can be controlled as a narrow width of below 1 .mu.m. Drain voltage is decreased due to the reduction of the offset regions' width. The effect of an increased parallel resistance and a bias voltage dependency of an overlap capacitance due to the arrangement of low concentration ion region reduces leakage current and improves the response to applied voltages. Also, gate voltage is decreased due to the decreased gate resistance when the polysilicon of the gate is substituted with the silicide.

REFERENCES:
patent: 4908326 (1990-03-01), Ma et al.
patent: 4971922 (1990-11-01), Watabe et al.

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