Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-11-27
2004-05-18
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C254S321000
Reexamination Certificate
active
06737344
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a nonvolatile semiconductor memory. More specifically, the present invention relates to a method for manufacturing a nonvolatile semiconductor memory having a tunnel oxide film, floating gate, insulating film and control gate stacked in this order on a semiconductor substrate.
Conventionally, a nonvolatile semiconductor memory of this kind is manufactured according to a process order shown in
FIGS. 10A
to
10
C and
11
A to
11
C.
FIGS. 10A
to
10
C are cross sections in an X—X direction in FIG.
1
A.
FIGS. 11A
to
11
C are cross sections in a Y—Y direction in FIG.
1
A. Here,
FIG. 1A
is a plan view of a nonvolatile semiconductor memory according to an embodiment of the present invention, but
FIG. 1A
is also used to explain a conventional technique.
First, as shown in
FIGS. 10A and 11A
, a tunnel oxide film
2
having a thickness of 10 nm is formed on a semiconductor substrate
1
by thermal oxidation. Then, a first conductive layer
3
having a thickness of 100 nm is deposited. The first conductive layer
3
is composed of polysilicon as a material of a floating gate. Subsequently, the tunnel oxide film
2
and the first conductive layer
3
are patterned in stripes extending in the Y—Y direction. At this time, a size of the first conductive layer
3
in the X—X direction (channel direction) is set so as to match a size of the floating gate to be finally formed.
Subsequently, phosphorus (P) ion implantation is performed under conditions of an acceleration energy of 50 keV and a dose of 3.0×10
13
ions/cm
2
by using the first conductive layer
3
patterned in stripes as a mask so as to form an n-type low-concentration impurity diffusion layer
4
in a surface region of the semiconductor substrate
1
between the first conductive layers
3
.
Subsequently, photolithography is performed to form a photoresist (not shown) in stripes extending in the Y—Y direction. Arsenic (As) ion implantation is performed by using this photoresist and the first conductive layer 3 patterned in stripes as masks under conditions of an acceleration energy 15 keV and a dose of 4.5×10
15
ions/cm
2
so as to form an n-type high-concentration impurity diffusion layer
5
in the low-concentration impurity diffusion layer
4
. These impurity diffusion layers
4
,
5
are used as a source/drain region i.e. a bit line.
Subsequently, as shown in
FIG. 10B
, an interlayer insulating film
6
is deposited on these layers in a thickness exceeding the thickness of the first conductive layer
3
by the CVD method to sufficiently cover the first conductive layer
3
. Subsequently, an etchback is performed to planarize the surface of the interlayer insulating film
6
, and the interlayer insulating film
6
is so left as to be embedded between the first conductive layers
3
.
Subsequently, as shown in
FIGS. 10C and 11C
, a first insulating film
7
composed of, for example, an ONO film (oxide film
itride film/oxide film) is deposited and then a second conductive layer
8
composed of polysilicon having a thickness of 200 nm is deposited. Then, photolithography is performed to form a photoresist (not shown) in stripes extending in the X—X direction. The second conductive layer
8
, the first insulating film
7
and the first conductive layer
3
are etched and patterned by using this photoresist as a mask. Consequently, there are formed a control gate in stripes composed of the second conductive layer
8
, the first insulating film
7
in stripes composed of the ONO film and a floating gate in a rectangular solid composed of the first conductive layer
3
.
In this state, as shown in
FIG. 12A
which is an enlarged view of a portion P enclosed with a broken line in
FIG. 11C
, a portion of the tunnel oxide film
2
immediately below a sidewall of the floating gate
3
includes damages (shown with x). This damaged portion easily serves as a path for electrons to leak from the floating gate
3
to the semiconductor substrate
1
side during an operation of a finished product. Accordingly, as shown in
FIG. 12B
, thermal oxidation is performed, for example, in an oxygen atmosphere at 850° C. for 20 minutes so as to form a silicon oxide film
11
having a thickness of 20 to 30 nm on the sidewalls of the floating gate
3
composed of polysilicon and the control gate
8
.
Subsequently, as shown in
FIG. 11C
, boron (B) ion implantation is performed under conditions of an acceleration energy 40 keV and a dose of 1.0×10
13
ions/cm
2
by using the control gate
8
as a mask so as to form a p-type element separating impurity diffusion layer
9
in a surface region of the semiconductor substrate
1
between the control gates
8
.
Then, an interlayer insulating film is deposited on this layer by a known method, a contact hole is opened in this interlayer insulating film and then interconnect lines are further formed to complete a nonvolatile memory, none of which are shown.
However, in the above conventional manufacturing method, as shown in
FIG. 7
which is an enlarged view of a portion P
1
enclosed with a broken line in
FIG. 12A
, a grain boundary
13
between polysilicon grains
12
of the floating gate
3
is easily oxidized during the process of oxidizing the sidewalls of the floating gate
3
and the control gate
8
because the silicon oxide film
11
is formed on the sidewalls of the floating gate
3
and the control gate
8
, resulting in localized nonuniform oxidation. As a result, a localized electric field concentration occurs between the floating gate
3
and the source/drain region in the semiconductor substrate
1
during an operation of the nonvolatile memory. Thus, a problem arises that equal FN (Fowler-Nordheim) currents do not flow through the tunnel oxide film in each memory cell during a write operation, thereby increasing a variation in threshold voltages between the memory cells.
As known, usually, data is simultaneously written in memory cells on the same word line (control gate). As evident from
FIG. 9
showing a threshold voltage distribution after a write operation in memory cells on the same word line, there is a large variation of 2.2 V in threshold voltages among nonvolatile memory cells on the same word line, which cells are manufactured by the above method.
In order to even the threshold voltages during a write operation, a verify write operation for each bit is usually performed. However, when there is a large variation in threshold voltages among memory cells on the same word line as described above, the number of steps during the write operation needs to be increased, resulting in a longer write time.
Furthermore, when data is written in this semiconductor memory, a high voltage is also applied to a nonselected memory cell on the same word line. Therefore, electrons in a floating gate of the nonselected cell are decreased (gate disturbance). When the variation in threshold voltages is large among memory cells on the same word line, a memory cell in which data can be particularly rapidly written is easily affected by the gate disturbance.
To solve the above problem, as shown in
FIG. 13
, a technique has been proposed wherein a tunnel oxide film
24
, a floating gate electrode
25
and a source region
22
are formed on the semiconductor substrate
21
, thereafter a material of the floating gate electrode
25
is isotropically etched and then oxidized (Japanese Patent Laid-Open Publication H9-17890). With this technique, a corner portion of the floating gate
25
on the semiconductor substrate
21
is made round while an oxide film
28
is formed. However, this technique cannot control the localized nonuniform oxidation attributable to polysilicon grains constituting the floating gate electrode
25
. As a result, an electric field concentration cannot be prevented and a variation in FN currents occurs for each memory cell and the variation in threshold voltages between memory cells is increased. Furthermore, since controlling of an etching rate in the isotropic etching pro
Yamagata Satoru
Yoshimi Masanori
Calvin Lee
Everhart Caridad
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
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