Method for manufacturing multi-level interconnections with...

Details Method for manufacturing multi-level interconnections with... Method for manufacturing multi-level interconnections with...

2006-02-07

2006-02-07

Huff, Mark P. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C430S314000, C430S316000, C430S317000, C438S584000, C438S624000, C438S637000, C438S700000

Reexamination Certificate

active

06994949

ABSTRACT:
A dual damascene process is disclosed which reduces capacitance increases caused by excess and unnecessary remnants of an etching stop layer and which also improves multi-level interconnect structures by removing the etching stop layer except for a portion that surrounds the via hole. This reduces or eliminates capacitance increase and avoids erosion of underlying interlayer insulating layers during formation of an upper, wider trench.

REFERENCES:
patent: 6042999 (2000-03-01), Lin et al.
patent: 6093632 (2000-07-01), Lin
patent: 6180514 (2001-01-01), Yeh et al.
patent: 6268283 (2001-07-01), Huang
patent: 6737350 (2004-05-01), Akahori et al.

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