Fishing – trapping – and vermin destroying
Patent
1995-08-31
1997-07-08
Chaudhari, Chandra
Fishing, trapping, and vermin destroying
437 44, 437154, H01L 21266
Patent
active
056460546
ABSTRACT:
A high threshold voltage MOS transistor is described having a triple diffused drain structure in which low, medium and high concentration impurity layers overlap each other. The MOS transistor is manufactured according to a method including the steps of: forming a first photosensitive film pattern which partially exposes a region to be formed as a source or a drain on a semiconductor substrate on which a field oxide film is formed; implanting first impurity ions to a low concentration, thereby forming a low concentration impurity layer; removing the first photosensitive film pattern; forming a second photosensitive film pattern which partially exposes the region to be formed as a source or a drain; implanting second impurity ions to a medium concentration, thereby forming a medium concentration impurity layer; removing the second photosensitive film pattern; forming a gate insulation film and gate electrode on the resultant semiconductor substrate; forming a third photosensitive film pattern which partially exposes the region to be formed as a source or a drain on the semiconductor substrate; and implanting third impurity ions to a high concentration, thereby forming a high concentration impurity layer.
REFERENCES:
patent: 4843023 (1989-06-01), Chiu et al.
patent: 4990982 (1991-02-01), Omoto
patent: 5217910 (1993-06-01), Shimizu et al.
patent: 5328862 (1994-07-01), Goo
patent: 5496751 (1996-03-01), Wei et al.
Chaudhari Chandra
Samsung Electronics Co,. Ltd.
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