Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-05-06
2001-04-03
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S691000, C438S692000
Reexamination Certificate
active
06211067
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing a metal plug.
2. Description of Related Art
In general, a metal plug is formed by first etching an insulation layer to form an opening and then forming a conformal barrier layer over the insulation layer and the sidewalls of the opening. Next, metal is deposited to fill the opening and cover the barrier layer. Finally, that portion of the metallic layer above the barrier layer is removed so that a metal plug is formed inside the opening.
There are several methods to remove the metallic material above the insulation layer. For example, one method of forming a tungsten plug is to etch back a portion of the tungsten layer using fluoride-containing plasma. However, due to the high reactivity of fluoride plasma, the upper surface of the tungsten plug may cave in a little. Therefore, a difference in height of up to about 1000 Å between the tungsten plug surface and its neighboring barrier layer is possible.
A second method is to polish the barrier layer using a chemical-mechanical polishing (CMP) operation after the tungsten layer is etched back so that the degree of concavity on the upper surface of the tungsten plug is reduced. However, the barrier layer of a tungsten plug is usually a titanium nitride layer while the insulation layer is normally a silicon oxide layer. Since titanium nitride and silicon oxide are materials having similar polishing rates in a CMP operation, a portion of the oxide insulation layer on each side of the tungsten plug will also be removed after the titanium nitride barrier layer is removed. In other words, the tungsten plug will protrude above the oxide insulation layer after the polishing operation, and often can be as high as 1500 Å. Because of the concavity of plug surface and its protrusion above the insulation layer, only a rough surface can be formed. Subsequently, when a photolithographic operation is carried out to pattern out conductive lines, light will likely be defocused since the surface is rough. Consequently, shapes and positions of those conductive lines will be somewhat affected and product quality will be compromised.
An alternative method is to polish the tungsten layer using CMP at the very start, and then perform a CMP touch-up operation at a slower polishing speed thereafter. This method is able to obtain a highly planar tungsten plug surface with a maximum variation within a range of about 200 Å to 300 Å. However, the cost can be as high as US$ 35 per silicon wafer.
In light of the foregoing, there is a need to provide a method of manufacturing a metal plug that can lower the cost of production.
SUMMARY OF THE INVENTION
The invention provides a method for manufacturing a metal plug. The method includes the steps of providing a substrate having an insulation layer thereon, and then forming an opening in the insulation layer. Next, a conformal barrier layer is formed over the insulation layer and sidewalls of the opening. Thereafter, metal is deposited to fill the opening and cover the barrier layer, and then a first etching back operation of the metallic layer is performed. The metallic layer is etched to the barrier layer forming a metal plug. Subsequently, a second etching back operation is carried out to remove the exposed barrier layer above the insulation layer. Finally, the metal plug and the insulation layer are planarized.
According to the method of this invention, the metallic layer and the barrier layer above the insulation layer are first removed by etching before the entire insulation layer containing the metal plug is planarized using a chemical-mechanical polishing operation. The cost of production can be reduced to about US$ 4 to US$ 5 per silicon wafer. Moreover, production time is shortened, and hence productivity is increased considerably.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5164330 (1992-11-01), Davis et al.
patent: 5907787 (1999-05-01), Sato
patent: 5942449 (1999-08-01), Meikle
patent: 6140224 (2000-10-01), Lin
Everhart Caridad
Huang Jiawei
J C Patents
Taiwan Semiconductor Mfg. Co. Ltd.
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