Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Reexamination Certificate
2001-02-21
2003-01-14
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
C438S113000, C438S118000, C438S618000, C438S669000
Reexamination Certificate
active
06506631
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for manufacturing integrated circuits and a semiconductor wafer that can be used in the method according to the invention.
In the prior art, fabrication methods for manufacturing integrated circuits, in particular chip-size packages from semiconductor wafers are known in which, in a first step, circuit structures for a plurality of integrated circuits are manufactured on an active side of a semiconductor wafer. Then, the integrated circuits are divided up into so-called chips by sawing the semiconductor wafer into individual pieces at the edge areas of the integrated circuits. Contact is made with the chips in each case at so-called interposers that may be of a rigid or a flexible configuration. It is also conceivable to make contact with a chip on a so-called lead frame. The contact can be made with different contacting methods, for example with a wire contacting method, with a flip-chip contacting method or with a TAB contacting method.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for manufacturing integrated circuits and a semiconductor wafer which has integrated circuits which overcomes the above-mentioned disadvantages of the prior art methods of this general type, in which a simplified method for manufacturing integrated circuits is described.
With the foregoing and other objects in view there is provided, in accordance with the invention, a manufacturing method for forming integrated circuits. The method includes the steps of:
providing a semiconductor wafer having an active side with circuit structures for forming at least two integrated circuits;
providing at least one electrically insulating intermediate layer;
applying at least one electrically conductive conductor foil to the electrically insulating intermediate layer;
forming at least one through-opening in the electrically insulating intermediate layer, the at least one through-opening extends from an underside of the electrically conductive conductor foil to an underside of the electrically insulating intermediate layer;
applying the least one electrically insulating intermediate layer having the electrically conductive conductor foil to the active side of the semiconductor wafer;
forming conductor tracks from the electrically conductive conductor foil; and
dividing the semiconductor wafer into individual integrated circuits.
The method according to the invention ensures a simple way to manufacture integrated circuits. A relatively thick organic dielectric layer is first provided for compensating for expansion. The final conductor structure with large conductor cross sections is produced only at the wafer level of the semiconductor wafer. The basic principle is to laminate a copper foil onto the semiconductor wafer, form a contact between the copper foil and the chip terminals or the connecting contacts of the integrated circuits and only then implement rewiring using photolithographic and etching technology.
The resin cover for a solder stop masking of the terminals can then be provided. Finally, the application of solder balls and the cutting up of the semiconductor wafer into individual packages can be carried out, for example by sawing. Generally, in order to give the semiconductor chip a particularly level surface it is possible to accompany the application of the copper foil laminate with a suitable corresponding coating on the passive reverse side of the chip.
In a development of the invention, the step of applying the intermediate layer to at least one electrically conductive conductor foil is carried out before the step of applying the intermediate layer to the active side of the semiconductor wafer. This embodiment of the method according to the invention serves as a basis for variants in which the intermediate layer is completely manufactured together with the conductor foil before application to the semiconductor wafer. In these embodiments of the method according to the invention it is particularly advantageous that manufacturing steps which are carried out on the intermediate layer and on the conductor foil do not affect the integrated circuits on the semiconductor wafer.
Before the step of applying the intermediate layer to the active side of the semiconductor wafer it is possible to provide the step of making at least one through-opening in the intermediate layer, the through-opening being embodied in such a way that it extends from an underside of the conductor foil to the underside of the intermediate layer. Then, contact can be made with the conductor foil through the through-opening. The through-opening is preferably made with a laser method, which enables precise through-openings to be achieved.
In order to make contact with the conductor foil through the intermediate layer it is possible to introduce a conductive filler and connecting material such as a solder material into the through-opening, specifically in particular by an electrodeposition method. This ensures that the semiconductor wafer according to the invention is manufactured in a particularly cost-effective and reliable way.
The step of heating the solder material in the through-opening may be provided in order to make contact between the conductor foil and the contact points on the integrated circuits on the semiconductor wafer, and may specifically be provided after the application of the intermediate layer to the active side of the semiconductor wafer. When the solder material in the through-opening is heated, the solder material is melted and forms a conductive connection with the contact points provided on the semiconductor wafer. Such heating is preferably carried out at points on the conductor foil in the vicinity of the through-opening so that the effect of the heat on the semiconductor wafer according to the invention is particularly low.
In a modification of the embodiments of the method according to the invention given above it is also possible to introduce a conductive adhesive as the conductive filler and connecting material into the through-opening, specifically in particular by a doctor blade method. The provision of the conductive adhesive in the through-openings favors large-scale series fabrication of the semiconductor wafer according to the invention. Here, the step of curing the conductive adhesive in the through-openings may be provided after the step of applying the intermediate layer to the active side of the semiconductor wafer, and may specifically be provided in such a way that the conductive adhesive forms a conductive connection both with the conductor foil and with contact points provided on the semiconductor wafer. A particularly favorable connection between the semiconductor wafer, the intermediate layer and the conductor foil is obtained if the step of applying the intermediate layer to the active side of the semiconductor wafer is carried out with a lamination method, in particular with the application of pressure and heat.
With the foregoing and other objects in view there is further provided, in accordance with the invention, a second method for manufacturing integrated circuits. The method includes the steps of:
providing a semiconductor wafer having an active side with circuit structures for at least two integrated circuits;
applying at least one electrically insulating intermediate layer to the active side of the semiconductor wafer;
applying a solder material to contact points provided on the semiconductor wafer by an electro-deposition method or an electroless deposition;
applying at least one electrically conductive conductor foil to the electrically insulating intermediate layer, an application of the electrically conductive conductor foil to the electrically insulating intermediate layer being provided after an application of the electrically insulating intermediate layer to the active side of the semiconductor wafer;
forming conductor tracks from the electrically conductive conductor foil; and
dividing the semiconductor wafer into individual integrated circu
Berezny Nema
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Nguyen Tuan H.
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