Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1998-07-28
2001-01-30
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S398000, C438S238000, C438S240000, C438S253000, C438S381000, C438S393000
Reexamination Certificate
active
06180482
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a very-large-scale-integrated (VLSI) semiconductor device, and more particularly, to a method for manufacturing a capacitor for a VLSI semiconductor device. The present application is based on, and priority is claimed from, Korea Patent Application No. 97-36165, filed Jul. 30, 1997, which is incorporated herein by reference for all purposes.
2. Description of the Related Art
Recently, many efforts to increase capacitance within a limited cell area have been focused on using thin films of high dielectric constant material, e.g., a high dielectric constant material having a perovskite structure. In order to be useful as a high dielectric constant thin layer for a capacitor, a material must meet the following requirements: (1) low leakage current; (2) large dielectric constant; and (3) excellent step coverage.
A method for decreasing the leakage current level of a high dielectric constant thin film while improving the dielectric constant is disclosed by Hwang et al. in a thesis entitled “Deposition of Extremely Thin (Ba, Sr) TiO
3
Thin Films for Ultra-Large-Scale Integrated Dynamic Random Access Memory Application,” Appl. Phys. Lett. 67(19), Nov. 6, 1995. According to this thesis, after forming a lower electrode, a (Ba, Sr) TiO
3
(BST) film is deposited at a substrate temperature of 660° C. using a sputtering technique. Subsequently, the BST film is annealed under a nitrogen (N
2
) atmosphere at a temperature of 750° C. It has been known that leakage current of a capacitor decreases and dielectric constant is improved when the BST film is annealed under an N
2
atmosphere, since a potential barrier is formed between an electrode and a BST film. However, according to this thesis, since the BST film is deposited by sputtering technique, step coverage of the BST film is lowered to 50% or less.
Compared to the BST film formed by sputtering technique, a BST film formed by a chemical vapor deposition (CVD) method shows improved step coverage. However, as the chemical vapor deposition temperature for forming the BST film is increased, the step coverage of the BST film is reduced. Accordingly, the step coverage of the BST film which can be achieved is limited so long as the BST film is formed at a deposition temperature of 500° C. or more. On the other hand, when the BST film is formed at a temperature less than about 500° C., step coverage is improved while dielectric constant of the BST film is decreased.
A method for manufacturing a capacitor having a BST film with improved step coverage and dielectric constant, is disclosed by T. Kawahara et. al. in a thesis entitled “(Ba, Sr) TiO
3
[BST] Films Prepared by Liquid Source Chemical Vapor Deposition on Ru Electrode,” Jpn. J. Appl. Phys. Vol. 34, 1996, pp 5077-5082. According to this method, a lower electrode is formed on a semiconductor substrate. A first BST buffer film is then deposited on the electrode at a substrate temperature of about 420° C. and to a thickness of 50~60 Å. Subsequently, the first BST film is annealed at 700° C. under a nitrogen (N
2
) atmosphere. Successively, the substrate temperature is set again to 420° C., and a second BST film is deposited on the first BST film. Next, the substrate temperature is raised to 700° C. and the second BST film is annealed and crystallized. An upper electrode is then formed on the crystallized second BST film, thereby completing the capacitor. The capacitor formed in this way has improved electrical properties because the BST film is annealed at high temperature under an N
2
atmosphere, and the BST film step coverage is increased because the BST film is formed at low temperature. According to this method, however, a two-step process must be repeatedly performed, that is, a deposition step and an annealing step is sequentially repeated twice. Thus, the fabrication process is complex. To simplify the fabrication process, the BST film may be annealed at 700° C. under N
2
atmosphere immediately after forming the BST film by a single step. However, in this case, the leakage current of the capacitor is increased and the dielectric constant thereof is lowered.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a simplified method for manufacturing a capacitor which provides increased step coverage of a high dielectric film and improved electrical properties of the capacitor.
According to an aspect of the present invention for achieving the above object, a capacitor cell unit comprising a high dielectric film including an amorphous portion is formed on a semiconductor substrate. Next, the capacitor cell unit is annealed to crystallize the high dielectric film amorphous portion.
The capacitor cell unit comprised of the high dielectric film including an amorphous portion is formed as follows. First, a first conductive film pattern is formed on a semiconductor substrate. A high dielectric film including an amorphous portion is formed on the first conductive film pattern. Next, a second conductive film is formed on the high dielectric film. The second conductive film and the high dielectric film are then sequentially patterned to form the capacitor cell unit.
The high dielectric film is formed by depositing the high dielectric material from a chemical vapor at a temperature where step coverage of the high dielectric film exceeds 80%. Alternatively, the high dielectric layer may be formed by sputtering. The temperature at which the step coverage exceeds 80% is 480°C. or less. As the high dielectric material, it is preferred to employ one selected from the group consisting of SrTiO
3
, (Ba, Sr)TiO
3
, PbZrTiO
3
, SrBi
2
Ta
2
O
9
, (Pb, La)(Zr, Ti)O
3
and Bi
4
Ti
3
O
12
. Also, the first conductive film pattern and the second conductive film are preferably formed of a material resistant to oxidation, i.e., a platinum group metal or an oxide thereof. The crystallization of the high dielectric film amorphous portion is achieved by annealing the capacitor cell unit at 500~800° C. under a non-oxidizing atmosphere.
According to the present invention, improved step coverage is achieved by depositing the high dielectric film at a temperature where step coverage exceeds 80%. After forming an upper electrode, the resultant structure is annealed under a non-oxidizing atmosphere, thereby crystallizing the amorphous portion of the high dielectric film. The dielectric constant of the high dielectric film is thereby increased and the leakage current of the capacitor is decreased. Since the amorphous portion of the high dielectric film is crystallized by a single-step annealing process, the fabrication process is simplified.
These objects aspects of the invention will be described in greater detail by reference to the drawings.
REFERENCES:
patent: 5390072 (1995-02-01), Anderson et al.
patent: 5587870 (1996-12-01), Anderson et al.
patent: 5626728 (1997-05-01), Ramakrishnan et al.
patent: 5843829 (1998-12-01), Kuramae et al.
patent: 5985676 (1999-11-01), New
Takaaki Kawahara et al., (Ba, Sr) Ti03 Films Prepared by Liquid Source Chemical Vapor Deposition on Ru Electrodes, Jpn J Appl Phys., vol. 35 (1996), pp. 4880-4885.
Cheol-Seong Hwang et al., Deposition of extremely thin (Ba,Sr) Ti03 thin films for ultra-large-scale integrated dynamic random access memory application, American Institute of Physics, (1995) pp. 2819-2821.
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Smith Matthew
Yevsikov Victor
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