Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-06-27
2003-02-04
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S585000, C438S591000
Reexamination Certificate
active
06514841
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly, to a method for manufacturing a gate structure for use in a semiconductor device by forming a diffusion barrier layer through a rapid thermal annealing process after patterning the gate structure.
DESCRIPTION OF THE PRIOR ART
Generally, a polysilicon is used for forming a word line in a semiconductor device and the word line is formed in a stack scheme. As a result, methods have been proposed for forming the word line with the stack scheme according to a method for forming a diffusion barrier layer which prevents an inter-diffusion of silicon atoms between the polysilicon layer and a gate electrode. In particular, a double layer provided with a polysilicon layer and a tungsten (W) layer is popularly used for the word line with a stack scheme.
FIGS. 1A and 1B
are cross sectional views setting forth a conventional method for forming the word line. To begin, a gate oxide layer
12
, a polysilicon layer
13
, a diffusion barrier layer
14
and then a tungsten (W) layer
15
are formed on a semiconductor substrate
11
, as shown in FIG.
1
A.
Thereafter, a hard mask of a nitride layer is formed on the tungsten layer
15
and then patterned into a predetermined configuration, thereby obtaining a hard mask pattern
16
. Subsequently, the tungsten layer
15
, the diffusion barrier layer
14
, the polysilicon layer
13
and the gate oxide layer
12
are patterned into the predetermined configuration, thereby obtaining a gate structure provided with a patterned gate oxide layer
12
A, a patterned polysilicon layer
13
A, a patterned diffusion barrier layer
14
A and a patterned tungsten layer
15
A, as shown in FIG.
1
B.
Conventionally, the gate structure incorporating therein the diffusion barrier layer
14
is formed by one of three methods, wherein the first method is to form the gate structure using a W/WN
x
(tungsten nitride) or TiN (titanium nitride) stack scheme, the second method is to form the gate structure using a denuded W scheme and the third method is to form the gate structure using a low temperature W scheme.
In the first method of the W/WN
x
or TiN scheme, a WN
x
layer or a TiN layer and a W layer are formed on the polysilicon layer subsequently, wherein a thickness of the WN
x
layer or the TiN layer is approximately 100 Å and a thickness of the tungsten layer is approximately 800 Å. The WN
x
layer or the TiN layer is used as the diffusion barrier layer in order to prevent the inter-diffusion of silicon atoms between the W layer and the polysilicon layer. However, when using the W/TiN scheme, there are problems of a high sheet resistance and a bad gap-fill capability for depositing an interlayer dielectric (ILD) layer in a post-manufacturing step. Further, it is difficult to apply a selective oxidation process for the W/TiN scheme because the TiN has a poor oxidation characteristic. When using the W/WN
x
scheme, there is a disadvantage in that two chambers having tungsten targets are needed for depositing the W layer and the WN
x
layer, sequentially. And further, in order to deposit the W layer and the WNx layer successively in the same chamber, the tungsten nitride in the target should be removed, whereby many targets and dummy wafers are consumed.
The second method of the denuded W scheme is to form the WN
x
layer on the polysilicon layer. Then, a rapid thermal annealing (RTA) is carried out in an N
2
ambient so that nitrogen atoms diffuse out from the WN
x
layer. As a result, the WN
x
layer is changed into a W layer and a WSiN layer of the diffusion barrier layer is formed beneath the W layer. However, because the second method is carried out at a high temperature, e.g., 1,000° C. for decreasing the sheet resistance, characteristics of the semiconductor device may be degraded eventually.
In the third method of the low temperature W scheme, after forming the W layer on the polysilicon layer, the RTA process is carried out in an NH
3
ambient, thereby obtaining a WSiN layer as the diffusion barrier layer between the W layer and the polysilicon layer. But this scheme is highly dependent upon the suitability of the structure of the polysilicon layer. For example, if the polysilicon layer has an amorphous structure, a tungsten silicide (WSi
x
) is apt to be formed and grown up during a post thermal treatment. Therefore, the electrical property of the gate electrode is degraded because the tungsten silicide has a higher resistivity than that of pure tungsten. In addition, if the polysilicon layer has a polycrystalline structure, the tungsten silicide also may be formed at a pattern edge of a gate structure and be grown up during the thermal treatment. Thus, derivability of the semiconductor device is degraded eventually.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for manufacturing a gate structure for use in a semiconductor device with stabilized derivability by forming a diffusion barrier layer through a rapid thermal annealing process after patterning the gate structure.
In accordance with one aspect of the present invention, there is provided a method comprising steps of a) forming a gate oxide layer, a polysilicon layer, a tungsten layer and a nitride layer on top of a semiconductor substrate, sequentially; b) patterning the nitride layer, the tungsten layer, the polysilicon layer and the gate oxide layer into a predetermined configuration; and c) carrying out a rapid thermal annealing (RTA) in an NH
3
ambient, thereby forming a diffusion barrier layer between a patterned tungsten layer and a patterned polysilicon layer.
REFERENCES:
patent: 6277719 (2001-08-01), Chern et al.
patent: 6303483 (2001-10-01), Kunikiyo
patent: 6362086 (2002-03-01), Weimer et al.
patent: 6444592 (2002-09-01), Ballantine et al.
patent: 2002/0072209 (2002-06-01), Tseng
Kim Yong-Soo
Oh Su-Jin
Hyundai Electronics Industries Co,. Ltd.
Jacobson & Holman PLLC
Pham Long
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