Method for manufacturing fusible links in a semiconductor...

Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state

Reexamination Certificate

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Reexamination Certificate

active

06210995

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for manufacturing electrically fusible links in VLSI circuits; and, more particularly, to a method for manufacturing fusible links having a cavity for accommodating a fused material.
DESCRIPTION OF THE PRIOR ART
In a typical integrated circuit, a large number of semiconductor devices may be fabricated on a silicon substrate. To achieve the desired functionality, a plurality of conductors are typically provided to couple selected devices together. In some integrated circuits, some of the conductive links may be coupled to fuses, which may be cut or blown after fabrication using lasers. In a dynamic random access memory (DRAM) circuit, for example, fuses may be employed during manufacturing to protect some of the transistors' gate stacks from destruction due to inadvertent built-up charges. Once fabrication of the IC is substantially complete, the fuses may be blown or cut to permit the DRAM circuit to function as if the protective current paths never existed. More commonly, fuses may be employed to set the enable bit and the address bits of a redundant array element in a DRAM circuit. To facilitate discussion,
FIG. 1
illustrates a typical dynamic random access memory (DRAM) integrated circuit, including a main memory array
202
. To facilitate replacement of a defective main array element within main memory array
202
, a redundant array
204
is provided as shown. A plurality of fuses in fuse array
206
are coupled to redundant array
204
via a fuse latch array
208
and a fuse decoder circuit
210
. To replace a defective main memory array element, individual fuses in fuse array
206
may be blown or cut to set their values to either a “1” or a “0” as required by the decoder circuit. During operation, the values of the fuses in fuse array
206
are typically loaded into fuse latch array
208
upon power up. These values are then decoded by fuse decoder circuit
210
during run time, thereby facilitating the replacement of specific failed main memory array elements with specific redundant elements of redundant array
204
. Techniques for replacing failed main memory array elements with redundant array elements are well known in the art and will not be discussed in great detail here for brevity's sake. As mentioned earlier, the fuse links within fuse array
206
may be selectively blown or cut with a laser beam. Once blown by the laser beam, the fuse changes from a highly conductive state to a highly resistive, i.e., non-conductive state, i.e., a blown fuse inhibits current from flowing through and represents an open circuit to the current path.
High density dynamic random access memories (DRAM) are designed with memory cell redundancy. The redundant memory cells are incorporated therein to prevent the loss of entire memories in the event that a minor number of memory cells do not function. Activation of the redundant memory cells is accomplished by fusible links which are strategically placed throughout the memory. Activation of a fusible link results in the disabling of the defective memory cell, while enabling in its place a redundant memory cell.
The process of “blowing” fusible links is implemented by heating the fusible link which is to be blown. The heated fusible link melts or evaporates, creating an open circuit for replacing the defective memory cells with a functional cell.
The fusible links are made of aluminum, copper and other high conductive metal or metal alloy. The conductive fusible link generally has a central width portion which is smaller than the ends to reduce the amount of energy necessary to melt the fusible link to create an open circuit condition. A small necked down portion of the fusible link acts as a fuse and can be blown out by an over-current or an over-voltage selectively applied in order to each memory cell. Usually the fusible link is made of a thin film of refractory metal.
FIG. 2
shows a schematic of a typical DRAM cell having a field effect transistor(FET)
100
and a fusible link
200
. The gate
110
of the FET
100
acts as the wordline W/L
120
. A bitline B/L
170
is connected to one terminal of the fusible link
200
. The other terminal of the fusible link
200
is connected to the one terminal
140
, e.g., a source terminal, of the FET
100
, depending on the applications such as read and write operations. The other DRAM terminal
150
, e.g., a drain terminal, is referred to as a plate.
The fusible link will melt causing an increase in volume when it is blown. Since, however, the melted fusible link was conventionally constrained within the a protective layer to prevent deterioration, it has to form a path by itself resulting in only a very small separation of the melted fusible link end. This can cause unwanted shorts or low resistance.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an improved fusible link DRAM containing a cavity which contains the melted fusible link.
In accordance with one aspect of the present invention, there is a method for forming a cavity for a fusible link in a semiconductor device comprising the steps of:
applying an etchable material over and around a portion of the fusible link;
coating the etchable material with a protection layer;
forming an access abutting the etchable material through the protection layer;
removing the etchable material to leave a cavity; and refilling the access with a refilling material.


REFERENCES:
patent: 4169000 (1979-09-01), Riseman
patent: 4209894 (1980-07-01), Keen
patent: 4460914 (1984-07-01), Te Velde et al
patent: 4536948 (1985-08-01), Te Velde et al.
patent: 4774561 (1988-09-01), Takagi
patent: 4879587 (1989-11-01), Jerman et al.
patent: 5291434 (1994-03-01), Kowalski
patent: 5585662 (1996-12-01), Ogawa
patent: 5641701 (1997-06-01), Fukuhara et al.
patent: 5679967 (1997-10-01), Janai et al.
patent: 03-04256 (1991-02-01), None
patent: 03-169049 (1991-07-01), None

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