Method for manufacturing field effect transistor

Details Method for manufacturing field effect transistor Method for manufacturing field effect transistor

2002-02-15

2004-12-21

Deo, Duy-Vu (Department: 1765)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S351000, C438S224000, C438S225000, C438S226000

Reexamination Certificate

active

06833589

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a field effect transistor (MOSFET: MOS Field Effect Transistor) having a very small gate length, which is achieved by using an SOI (silicon-on-insulator) substrate with a silicon layer formed on an insulating layer.
2. Description of the Related Art
An SOI substrate is constituted of an insulating layer and a silicon layer formed on the insulating layer. The structural features of the SOI MOSFET manufactured by using such an SOI substrate achieve advantages of a small parasitic capacitance, being latch-up free, a low soft error rate, relative ease in element isolation and the like. For this reason, an SOI MOSFET is considered to be ideal in application in a high-speed, low power consumption LSI.
In particular, since a depletion layer formed under a gate reaches a buried oxide film (BOX) under the SOI in a fully depleted (FD) device, the depletion layer capacitance can be reduced in the fully depleted device. Thus, an advantage is achieved in that the sub-threshold slope can be reduced to a value very close to the ideal value.
The SOI MOSFET manufacturing methods in the related art include the SOI nMOSFET manufacturing method disclosed in “T, Ohno et al., IEEE Trans. On Electron Devices, 42, p.1481, 1995” (hereafter referred to as the “first related art method”). In the first related art method, a field oxide film for element isolation is first formed on an SIMOX (Separation by Implanted Oxygen) substrate achieved by forming a buried oxide film and a silicon layer on a silicon substrate at 100 nm and 56 nm respectively. Next, boron fluoride (BF
2
) ions are implanted into a body area enclosed by the field oxide film until a concentration of approximately 10
17
cm
−3
is achieved. Then, ions of an impurity, i.e., BF
2
, are implanted for channel stopping at the edge of the body area. As a result, a higher density is achieved at the edge of the silicon layer.
In the next step, a gate oxide film is formed over a thickness of 7 nm on the body area. Then, N
+
polysilicon is formed over a 30 nm thickness on the gate oxide film and the area ranging from one side of the field area through the center of the body area to the opposite side of the field area is patterned to form a gate electrode having a gate length of approximately 0.25 &mgr;m.
In the following step, a silicon nitride (SiN) film and an N
+
polysilicon film are formed at the side surface of the gate electrode constituted of the N
+
polysilicon and a sidewall constituted of the SiN film and the N
+
polysilicon film are formed through sidewall etching.
Then, phosphorus (P) is injected into the edge of the silicon layer through ion implantation to form a source drain area.
Next, after removing the N
+
polysilicon film alone through wet-etching from the sidewall thereby achieving a sidewall exclusively constituted of the SiN film, a rapid thermal annealing treatment (RTA; rapid thermal anneal) is performed at 1000° C. in order to activate the impurities.
A fully depleted SOI field effect transistor (MOSFET) achieving a very small gate length is manufactured through the first related art method as described above. In the first related art method, the threshold voltage (Vth) of the parasitic transistor formed at the edge of the body area is raised by implanting channel-stopping ions, and thus, a reduction in the off-leak current attributable to the occurrence of a hump is attempted.
Another SOI MOSFET manufacturing method in the related art is disclosed in “Naka et al. Shingaku Giho, SDM 96-234, p.45, 1997” (hereafter referred to as the “second related art method”).
The second related art method utilizes an SIMOX wafer achieved by forming a buried oxide film and a silicon layer over 100 nm and 55 nm respectively on a silicon substrate. A field oxide film for element isolation is formed first. Next, boron fluoride (BF
2
) and phosphorus (P) are injected into two body areas to constitute an nMOS and a pMOS through ion implantation to a concentration achieving a threshold voltage of 0.2~0.3 V.
Then, a gate oxide film is formed over a thickness of 7 nm on the two body areas. A non-doped polysilicon is formed over a thickness of 200 nm on the gate oxide film and then a gate electrode having a gate length of approximately 0.35 &mgr;m are formed through patterning.
In the following step, a sidewall constituted of a silicon oxide (SiO
2
) film is formed at part of each body area, and then P and BF
2
are injected into the nMOS area and the pMOS area through ion implantation. A single drain of the n MOSFET and pMOSFET are formed as a result. At the same time, an impurity is doped at each gate electrode. As a result, an N
+
polysilicon gate electrode and a P
+
polysilicon gate electrode are formed respectively at the nMOS area and the pMOS area.
In the next step, furnace annealing is performed at 800° C. and then an RTA is performed at 1000° C. to activate the impurities. Afterwards, a Ti silicide is formed on the source•drain and also on the gate through a Ti silicide process.
A fully depleted SOI field effect transistor (CMOSFET) having a very small gate length is obtained through the second related art method as described above. The transistor obtained through this method, in which only a single source•drain ion implantation each is implemented for the nMOS area and the pMOS area, has a “single drain” structure.
While there is no detailed description in the publication, it is necessary to implement a photolithography process to implant ions at the edge of the nMOS body area for channel stopping in the first related art method.
FIG. 17
illustrates the relationship between the gate electrode and the body area where the source•drain are formed in a view taken from above the element. The two areas enclosed by the dotted lines in
FIG. 17
indicate the edge of the body area where ions need to be implanted for channel stopping.
When implanting ions after a photolithography process, it is necessary to allow for an “alignment margin” between the active area and the resist pattern where channel-stopping ion implantation is to be implemented.
FIG. 18
shows the relationship between the active area and the resist pattern provided for channel-stopping ion implantation. As shown in
FIG. 18
, the width of the resist pattern constitutes the effective gate length. This means that the effective gate length is represented by the value obtained by subtracting the dimension required as the alignment margin from the dimension of the active area width. As miniaturization of elements is pursued with increasing vigor, the alignment margin is bound to become equal to or larger than the effective gate length. Accordingly, the first related art method poses a problem in that when attempting to reduce the element size, the width of the active area cannot be reduced.
FIG. 19
is a sectional view of an element formed at an SOI substrate having a silicon layer formed over an insulating layer. It shows an area (A) where channel stopping is required, an area (B) where channel stopping is not required and an area (C) where channel stopping ions have not been implanted. The area (A) where a high impurity concentrations must be achieved through channel stopping ion implantation is the hatched area in the sectional view presented in
FIG. 19
where the film thickness of the silicon layer is reduced ranging over approximately 50 nm from the edge of the body area. In this area, the gate oxide film constituted of the field oxide film has a large thickness. However, since the film thickness of the silicon layer is small, the quantity of the impurity contained in the silicon layer is smaller than the quantity in the area with a larger film thickness. This results in a lowered threshold voltage of the parasitic transistor which manifests hump characteristics shown in FIG.
20
. In
FIG. 20
, the vertical axis represents the drain current (Ids), the horizontal axis represents the gate voltage (Vg),

Affiliated with

Also associated with

Rating

Method for manufacturing field effect transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing field effect transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing field effect transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3332251